Abstract: Apparatus for enabling access to Flash random access memory devices at substantially the same bandwidth and speed for both reading and writing. A plurality of processors can be dynamically and/or statically configured into separate portions to handle reading and writing actions. One portion can be arranged to separately handle interfacing with high speed connections to receive and respond to read and write commands from an external system. The second portion can be arranged to handle high speed access over an interface that can both read serially and write in parallel to the Flash random access memory device. By writing in parallel to the Flash random access memory device with multiple processors, the write mode is at least somewhat equivalent to or greater than the speed and bandwidth for a serial read of the memory device.