Abstract: A method and apparatus for optimization of a modem for high data rate applications comprise a plurality of hardware accelerators which are configured to perform data processing functions, wherein the hardware accelerators are parameterized, a processor is configured to selectively activate accelerators according to the desired function to conserve power requirements and a shared memory configured for communication between the plurality of hardware accelerators.

Abstract: A physical layer transport composite processing system used in a wireless communication system. A plurality of interconnected processing blocks are provided. The blocks are interconnected by a read data bus, a write data bus and a control bus. The blocks include a transport channel processing block, a composite channel processing block and a chip rate processing block. At least two of the blocks are capable of processing data for a plurality of wireless formats. A first set of parameters is programmed into the blocks for a particular wireless mode. The blocks are operated to process data in the particular wireless format mode.

Abstract: The invention includes various embodiments for use in physical layer processing. One embodiment determines the address mapping of bits in the physical channel buffer from the address of bits in the first interleaver buffer. The physical channel buffer addresses are determined corresponding to addresses of the bits after rate matching, bit scrambling, second interleaving and physical channel mapping. The bits are directly read from the first interleaver buffer and written to the physical channel buffer using the determined physical channel buffer addresses. Another embodiment determines the address mapping of bits in the first interleaver buffer from the address of bits in the physical channel buffer. The first interleaver buffer addresses are determined corresponding to addresses of the bits after reverse rate matching, reverse bit scrambling, reverse second interleaving and reverse physical channel mapping.

Abstract: The invention includes various embodiments for use in physical layer processing. One embodiment determines the address mapping of bits in the physical channel buffer from the address of bits in the first interleaver buffer. The physical channel buffer addresses are determined corresponding to addresses of the bits after rate matching, bit scrambling, second interleaving and physical channel mapping. The bits are directly read from the first interleaver buffer and written to the physical channel buffer using the determined physical channel buffer addresses. Another embodiment determines the address mapping of bits in the first interleaver buffer from the address of bits in the physical channel buffer. The first interleaver buffer addresses are determined corresponding to addresses of the bits after reverse rate matching, reverse bit scrambling, reverse second interleaving and reverse physical channel mapping.

Abstract: A method and apparatus for adaptively biasing a channel quality indicator (CQI) used for setting a configuration of communication between a transmitter and a receiver in a wireless communication system. The receiver sends a CQI and positive acknowledgement (ACK)/negative acknowledgement (NACK) messages to the transmitter. The ACK/NACK messages indicate the absence or presence of error, respectively, in a transmitted data packet. The CQI is derived from the signal-to-interference ratio (SIR) and the ACK/NACK messages. The transmitter calculates the block error rate (BLER) of the transmitted data packets based upon the ACK/NACK messages sent from the receiver. The transmitter compares the BLER of the transmitted data packets to a target BLER and biases the CQI based on the comparison in order to achieve the target BLER.

Abstract: A physical layer transport composite processing system used in a wireless communication system. A plurality of interconnected processing blocks are provided. The blocks are interconnected by a read data bus, a write data bus and a control bus. The blocks include a transport channel processing block, a composite channel processing block and a chip rate processing block. At least two of the blocks are capable of processing data for a plurality of wireless formats. A first set of parameters is programmed into the blocks for a particular wireless mode. The blocks are operated to process data in the particular wireless format mode.

Abstract: A method and apparatus for adaptively biasing a channel quality indicator (CQI) used for setting a configuration of communication between a transmitter and a receiver in a wireless communication system. The receiver sends a CQI and positive acknowledgement (ACK)/negative acknowledgement (NACK) messages to the transmitter. The ACK/NACK messages indicate the absence or presence of error, respectively, in a transmitted data packet. The CQI is derived from the signal-to-interference ratio (SIR) and the ACK/NACK messages. The transmitter calculates the block error rate (BLER) of the transmitted data packets based upon the ACK/NACK messages sent from the receiver. The transmitter compares the BLER of the transmitted data packets to a target BLER and biases the CQI based on the comparison in order to achieve the target BLER.

Abstract: A physical layer transport composite processing system used in a wireless communication system. A plurality of interconnected processing blocks are provided. The blocks are interconnected by a read data bus, a write data bus and a control bus. The blocks include a transport channel processing block, a composite channel processing block and a chip rate processing block. At least two of the blocks are capable of processing data for a plurality of wireless formats. A first set of parameters is programmed into the blocks for a particular wireless mode. The blocks are operated to process data in the particular wireless format mode.

Abstract: The invention includes various embodiments for use in physical layer processing. One embodiment determines the address mapping of bits in the physical channel buffer from the address of bits in the first interleaver buffer. The physical channel buffer addresses are determined corresponding to addresses of the bits after rate matching, bit scrambling, second interleaving and physical channel mapping. The bits are directly read from the first interleaver buffer and written to the physical channel buffer using the determined physical channel buffer addresses. Another embodiment determines the address mapping of bits in the first interleaver buffer from the address of bits in the physical channel buffer. The first interleaver buffer addresses are determined corresponding to addresses of the bits after reverse rate matching, reverse bit scrambling, reverse second interleaving and reverse physical channel mapping.