Abstract: An analog signal is transported across an isolation channel using edge modulation/demodulation of a pulse width modulated (PWM) signal. An edge modulator is responsive to rising edges of the PWM signal to generate first pulses having a first predetermined pulse width and is responsive to receipt of falling edges of the PWM signal to generate second pulses having a second predetermined pulse width with the same polarity as the first pulses. On the opposite side of the isolation channel an edge demodulating circuit recreates the PWM signal using the first and second pulses. The rise and falling edges of the PWM signals can be distinguished based on the pulse width of the first and second pulses. A second order pulse width modulator may be used to generate the PWM signal.

Abstract: An analog signal is transported across an isolation channel using edge modulation/demodulation of a pulse width modulated (PWM) signal. An edge modulator is responsive to rising edges of the PWM signal to generate first pulses having a first predetermined pulse width and is responsive to receipt of falling edges of the PWM signal to generate second pulses having a second predetermined pulse width with the same polarity as the first pulses. On the opposite side of the isolation channel an edge demodulating circuit recreates the PWM signal using the first and second pulses. The rise and falling edges of the PWM signals can be distinguished based on the pulse width of the first and second pulses. A second order pulse width modulator may be used to generate the PWM signal.

Abstract: A linefeed driver apparatus includes a first current mirror having an input leg for current IIN1 and a mirrored leg for current IMIRR1, wherein IMIRR1 varies proportionately to IIN1 with a gain of ?1. The input leg and the mirrored leg of the first current mirror are coupled to provide (?1+1)IIN1 to a driven line. The apparatus includes a second current mirror having an input leg for current IIN2 and a mirrored leg for current IMIRR2, wherein IMIRR2 varies proportionately to IIN2 with a gain of ?2. The mirrored leg of the second current mirror provides ?2IIN2 to the driven line, wherein ?2=?1+1.

Abstract: One embodiment of an apparatus for switching a transistor includes a first current mirror providing iB=K1i1, as a transistor base current, wherein the first current mirror is selectively driven by a current source i B ? ? MAX K 1 . A second current mirror providing a feedback signal i2=K2iD to the first current mirror such that i 1 + i 2 = i B ? ? MAX K 1 , wherein iD contributes to the transistor collector current, wherein iB=iBMAX?K1K2iD.

Abstract: One embodiment of a power supply apparatus includes a switching regulator generating an output voltage VOUT at an output node from an input voltage VIN at an input node in accordance with a pulse width modulated signal having a nominal frequency of fs. A pulse width modulator provides the pulse width modulated signal in accordance with a pulse control signal. A digital control loop sampling the second voltage to provide an m-bit sampled value at a sampling rate, f1. The digital control loop includes a loop filter providing a filtered value from the sampled value and a delta sigma modulator sampling the filtered value as an n-bit value at a frequency f2 to provide the pulse control signal, wherein m>n.

Abstract: A switching regulator apparatus includes an inductor coupling an input node to a switching node. A first capacitor couples the switching node to a diode node. A first diode couples the diode node to a common node. A second diode couples the diode node to an output node. A second capacitor couples the output node to the common node. A switch couples the switching node to the common node, wherein the first capacitor transfers energy from the input node to the output node in accordance with the commutation of the switch.

Abstract: One embodiment of an apparatus for switching a transistor includes a first current mirror providing iB=K1i1, as a transistor base current, wherein the first current mirror is selectively driven by a current source i B ? ? MAX K 1 . A second current mirror providing a feedback signal i2=K2iD to the first current mirror such that i 1 + i 2 = i B ? ? MAX K 1 , wherein iD contributes to the transistor collector current, wherein iB=iBMAX?K1K2iD.

Abstract: A phase-locked loop (PLL) achieves initial lock using a course fractional-N divider driving a binary phase detector. Once frequency lock is achieved, this divider may be turned off, while an adaptive phase detector takes over control of the PLL front end. The adaptive phase detector (APD) receives input directly from the VCO and the reference clock, deriving digital control signals and a precision phase detector output. The APD operates at the update rate, generating a digital delta sigma modulator (DSM) data stream output at the update rate. The APD automatically locks to a digitally generated ramp corresponding to an expected difference between the VCO output and the reference clock, while adaptively correcting for DC errors and ramp cancellation errors.

Abstract: A phase-locked loop (PLL) achieves initial lock using a course fractional-N divider driving a binary phase detector. Once frequency lock is achieved, this divider may be turned off, while an adaptive phase detector takes over control of the PLL front end. The adaptive phase detector (APD) receives input directly from the VCO and the reference clock, deriving digital control signals and a precision phase detector output. The APD operates at the update rate, generating a digital delta sigma modulator (DSM) data stream output at the update rate. The APD automatically locks to a digitally generated ramp corresponding to an expected difference between the VCO output and the reference clock, while adaptively correcting for DC errors and ramp cancellation errors.

Abstract: A noise cancellation signal is generated for a fractional-N phase-locked loop (200). A divide value is provided to a first delta sigma modulator circuit (203), which generates a divide control signal to control a divide value of a feedback divider (208) in the phase-locked loop. An error term (e) is generated that is indicative of a difference between the generated divide control signal and the divide value supplied to the first delta sigma modulator circuit. The error term is integrated in an integrator (320) to generate an integrated error term (x), where xk+1=xk+ek; and a phase error correction circuit (209) utilizes the error term ek and the integrated error term xk to generate the phase error cancellation signal.

Abstract: An apparatus for offloading power includes a power offload element providing a supply drop from a first supply level to a second supply level. The supply drop varies in response to a control signal. A signal processor of a subscriber line interface circuit provides the control signal. A linefeed driver of the subscriber line interface circuit is coupled to receive the second supply level for driving a subscriber line.

Abstract: A linear amplifier architecture includes first, second, and third stages. The first stage is a transconductance stage. The third stage is a current amplification stage. The second stage is an interfacing stage between the first and third stages. The interfacing stage provides a voltage bias and a current to the third stage. The linear amplifier is a class AB amplifier. Quiescent currents for the output devices of the third stage are controlled by the second stage. The stages may be fabricated on the same semiconductor substrate. In one embodiment, the amplifier is fabricated as a complementary metal oxide semiconductor (CMOS) integrated circuit using metal oxide semiconductor field effect transistors (MOSFET). In one application, the amplifier serves as a component of a driver circuit for a subscriber line. Electrostatic discharge (ESD) protection circuitry provided for the amplifier may also be suitable for other applications.

Abstract: A digital-to-analog converter circuit for a subscriber line analog front end includes a differential amplifier, switch circuitry, and first and second current steering digital-to-analog converters (DAC), each DAC having a first and second output forming a differential DAC output. The switch circuitry couples the differential output of at most a selected one of the first and second DACs to a pair of switch nodes. When the differential output of the selected DAC is coupled to the pair of switch nodes, the differential output of the other DAC is shorted. A differential input of the differential amplifier is communicatively coupled to the pair of switch nodes. A differential output of the differential amplifier is coupled to drive a tip line and a ring line of a subscriber line. In various embodiments, the DACs, switch circuitry, and differential amplifier reside on the same semiconductor substrate.

Abstract: A digital-to-analog converter circuit for a subscriber line analog front end includes a differential amplifier, switch circuitry, and first and second current steering digital-to-analog converters (DAC), each DAC having a first and second output forming a differential DAC output. The switch circuitry couples the differential output of at most a selected one of the first and second DACs to a pair of switch nodes. When the differential output of the selected DAC is coupled to the pair of switch nodes, the differential output of the other DAC is shorted. A differential input of the differential amplifier is communicatively coupled to the pair of switch nodes. A differential output of the differential amplifier is coupled to drive a tip line and a ring line of a subscriber line. In various embodiments, the DACs, switch circuitry, and differential amplifier reside on the same semiconductor substrate.

Abstract: A method of tuning a DCXO includes the step of providing a coarse tuning array and a fine tuning array of capacitors fabricated on the same integrated circuit die. The coarse array is adjusted until the difference between a desired frequency and the output frequency corresponds to a change in capacitance no greater than half the range of the fine tuning array. In one embodiment, the fine tuning array is adjusted to mid-range before adjusting the coarse tuning array. A DCXO apparatus includes at least one integrated circuit segmented switched capacitor network providing a capacitance that is a nonmonotonic function of a composite input code. The segmented switched capacitor network includes parallel coupled binary weighted and thermometer coded switched capacitor networks for coarse and fine tuning, respectively.

Abstract: A linear amplifier architecture includes first, second, and third stages. The first stage is a transconductance stage. The third stage is a current amplification stage. The second stage is an interfacing stage between the first and third stages. The interfacing stage provides a voltage bias and a current to the third stage. The linear amplifier is a class AB amplifier. Quiescent currents for the output devices of the third stage are controlled by the second stage. The stages may be fabricated on the same semiconductor substrate. In one embodiment, the amplifier is fabricated as a complementary metal oxide semiconductor (CMOS) integrated circuit using metal oxide semiconductor field effect transistors (MOSFET). In one application, the amplifier serves as a component of a driver circuit for a subscriber line. Electrostatic discharge (ESD) protection circuitry provided for the amplifier may also be suitable for other applications.

Abstract: A method of tuning a DCXO includes the step of providing a coarse tuning array and a fine tuning array of capacitors fabricated on the same integrated circuit die. The coarse array is adjusted until the difference between a desired frequency and the output frequency corresponds to a change in capacitance no greater than half the range of the fine tuning array. In one embodiment, the fine tuning array is adjusted to mid-range before adjusting the coarse tuning array. A DCXO apparatus includes at least one integrated circuit segmented switched capacitor network providing a capacitance that is a nonmonotonic function of a composite input code. The segmented switched capacitor network includes parallel coupled binary weighted and thermometer coded switched capacitor networks for coarse and fine tuning, respectively.

Abstract: A digital-to-analog conversion circuit includes first and second DACs. Switch circuitry couples a selected output of only one of the DACs to an output node at any given time. In one embodiment, a second output of the first DAC is coupled to the first output of the second DAC at a common node. The first output of the first DAC is coupled to a first switch node and a second output of the second DAC is coupled to a second switch node. A first switch couples the common node to the first switch node in response to a first switch signal. A second switch couples the common node to the second switch node in response to a second switch signal. The switch signals ensure that the common node is coupled through the first and second switches to only one of the first and second switch nodes at any given time.

Abstract: A digital-to-analog conversion circuit includes first and second DACs. Switch circuitry couples a selected output of only one of the DACs to an output node at any given time. In one embodiment, a second output of the first DAC is coupled to the first output of the second DAC at a common node. The first output of the first DAC is coupled to a first switch node and a second output of the second DAC is coupled to a second switch node. A first switch couples the common node to the first switch node in response to a first switch signal. A second switch couples the common node to the second switch node in response to a second switch signal. The switch signals ensure that the common node is coupled through the first and second switches to only one of the first and second switch nodes at any given time.

Abstract: A signal conditioning circuit compresses an audio signal by producing a gain signal that is a function of the time-averaged audio signal and a compression ratio, and amplifying the audio signal by an exponential function of the gain signal. The conditioning circuit merges the functions of buffering the audio signal and producing a full-wave rectified version of the audio signal into a single buffer circuit. An averaging circuit generates a time-averaged signal in response to the full-wave rectified signal. An interface circuit includes downward expansion, compression and limiting circuits for scaling the time-averaged signal with a low compression ratio when it is less than a break point, with a selected compression ratio when it is between the break point and a rotation point, and with a high compression ratio when it exceeds the rotation point. The interface circuit produces the gain signal in response to the time-averaged signal and the corresponding compression ratio.