Abstract: A burst error scrubbing system and method consecutively detects and corrects errors in all of memory, beginning with data stored at the first address of memory and continuing until data stored at the last address of memory is read, corrected and written back to memory. Burst error scrubbing is not performed during a refresh cycle but instead is programmable so that the burst scrubbing can be performed at a specific time interval.

Abstract: A method and system for automatic configuration of memory devices having a same initial address. Initially, all of the memory devices in the computer system are disabled but one enabled memory device. An initial address of the enabled memory device is changed to a new unique address. Then, unless all of the memory devices have been enabled, one previously disabled memory device is enabled to produce a next enabled memory device having the initial address. The steps of changing the initial address of the enabled memory device to a new unique address and enabling a next enabled memory device having the initial address are then repeated until the initial address of each of the memory devices has been changed to a new unique address.

Abstract: A system including a number of circuit boards is provided that configures itself automatically. Any number of circuit boards can be placed in any order including sandwich arrangements where the circuit boards automatically configure themselves without any manual intervention by a skilled individual changing jumpers or strapping devices. The multi-board system removes the possibility of an error occurring while configuring the memory and registers.

Abstract: Two or more memory arrays are coupled to two or more error detection and correction (EDAC). Each memory array has a plurality of memory devices each having a plurality of outputs. The outputs of each memory are divided among the EDACs such that no more than two outputs from a single memory device are coupled to a single EDAC.

Abstract: A concurrent arbitration system and method are provided wherein the most recent requester retains control of a system resource under certain conditions and is allowed access to the resource during a portion of an arbitration cycle which will result in the granting of access to the resource by another requester. This overlapping of a resource access cycle and an arbitration cycle decreases the overall arbitration time and therefore reduces the overall resource access time.

Abstract: A circuit and method for implementing a predetermined data replacement algorithm associated with a fast, low capacity cache, such as least recently used (LRU), which is fast and which minimizes circuitry is provided. A latch stores the present status of the replacement algorithm, and an address control signal indicates which one of n sets of stored information in the cache has been most recently accessed, where n is an integer. The predetermined algorithm is implemented by a predetermined permutation table stored in a translator which provides an output signal in response to both the present status of the replacement algorithm and the address control signal. The output signal indicates which one of the n sets of stored information in the cache may be replaced with new information.

Abstract: An arbitration circuit for asynchronously arbitrating between refreshing memory and performing a non-refresh memory cycle in a memory system having memory cycle generating circuitry. Arbitration circuitry comprising logic circuitry, a clocked storage device and delay circuits which are coupled to memory cycle generating circuitry for performing an arbitration decision for a memory during an immediately preceding memory cycle. The arbitration circuitry time overlaps an arbitration operation with a memory cycle operation during a first memory cycle, thereby improving data rate for an adjacent second memory cycle.