Abstract: A timer on a microprocessor includes a vibrator formed by a comparator, a capacitor, three reference voltages, and switched current sources, which charge and discharge the capacitor. The vibrator oscillates at two different amplitudes to generate two timing windows, one at high amplitude and the other at low amplitude. A counter counts incoming clocks and times out after a fixed number of vibrator oscillations. Logic starts the timing windows and subtracts incoming clock measurements taken during the two timing windows. The logic subtraction cancels errors accumulated from the multiple ramps of the capacitor in the vibrator. The subtraction allows more precise measurement of incoming clocks. If the clocks counted exceed a threshold value, the microprocessor shuts down due to over clocking.

Abstract: A startup control voltage preset method and apparatus to reduce phase locked loop lock acquisition time at startup. In one embodiment, the disclosed apparatus includes a phase locked loop circuit including a startup circuit that is activated at startup. The startup circuit is coupled to force a control input of a voltage control oscillator of the phase lock loop circuit across a loop filter to a voltage at or near a target nominal operating voltage. In one embodiment, the target nominal operating voltage corresponds to a target operating frequency of the phase locked loop circuit. In one embodiment, the startup circuit is coupled to be activated for a predetermined time at startup. In one embodiment, the startup circuit is coupled to be activated at startup until the control input voltage of the voltage controlled oscillator is at or near a reference voltage.

Abstract: An apparatus and method for detecting and measuring internal clock jitter is disclosed. In one embodiment, a reference clock generator generates a reference clock signal based on an instantaneous clock signal. The reference clock signal includes the instantaneous clock signal delayed for an average duration. A phase comparing element receives both the instantaneous clock signal and the reference clock signal such that the phase comparing element measures a phase difference between the instantaneous clock signal and the reference clock signal. The magnitude and direction of the phase difference is indicated by one of a number of distinct phase difference bins in the phase comparing element.

Abstract: A method and an apparatus for biasing a charge pump in a phase locked loop in a circuit and generally for biasing a circuit through the use of a replica circuit. The method and apparatus make use of a replica circuit including substantially similar circuit elements to those circuit elements making up the circuit to be biased. Through the use of comparison and bias techniques, the replica circuit and the circuit to be biased are both biased. The bias conditions result from a comparison of the operation of the replica circuit and the circuit to be biased. Since the replica circuit operates in a manner substantially similar to an expected operation mode of the circuit to be biased, the bias conditions resulting from the comparisons will cause the circuit to be biased to operate similarly to how the replica circuit operates, while still handling external influences such as loading.