Abstract: An electronic interface circuit and method for receiving high speed serial ata, converting the data to parallel data and multiplexing different types of data together with a temporary buffer storage utilizing a First-In-First-Out (FIFO) buffer memory and controllable output interface circuits and signals is provided. Sources of the data can be, for example, a frame synchronizer used to process high speed data from a TIROS-N satellite. The circuitry of a specific embodiment includes line receivers for receiving the data and a controllable output register and line drivers for providing the output data. The input data includes a synchronizing clock signal and control signals and three types of data. A serial to parallel data converter converts the appropriate data and controllable tri-state buffers determine the sequence of providing the data to an internal data bus connected to the input of the FIFO memory.