Abstract: Systems and methods for routing packets around dead dies in an array are disclosed. In some embodiments, a method for routing a packet in a die array that include a dead die can include routing a packet from a first die to a second die by way a first channel of a plurality of first channels and routing the packet from the second die to a third die by way of a second channel of a plurality of second channels based on one or more routing rules. The one or more routing rules can allow the first channel to route the packet to a subset of the plurality of second channels that includes the second channel. The second channel can be orthogonal to the first channel such that routing the packet from the first die to the third die involves a turn. The method can route the packet around the dead die.

Abstract: This application relates to systems and methods for reduced latency in arrays of computing nodes. In some embodiments, a method of routing data can include outputting a first bypass signal and a second bypass signal from a first computing node of an array of computing nodes, wherein the first bypass signal indicates to route packet data through a second computing node and the second bypass signal indicates to turn the packet data in a third computing node. The packet can be routed through the second node based on the first bypass signal in a single clock cycle, and the packet can be routed from the second computing node to the third computing node in a single clock cycle. The second computing node receives the first bypass signal by way of a faster route than it receives the packet data.

Abstract: The techniques described herein provide an instruction fetch and decode unit having an operation cache with low latency in switching between fetching decoded operations from the operation cache and fetching and decoding instructions using a decode unit. This low latency is accomplished through a synchronization mechanism that allows work to flow through both the operation cache path and the instruction cache path until that work is stopped due to needing to wait on output from the opposite path. The existence of decoupling buffers in the operation cache path and the instruction cache path allows work to be held until that work is cleared to proceed. Other improvements, such as a specially configured operation cache tag array that allows for detection of multiple hits in a single cycle, also improve latency by, for example, improving the speed at which entries are consumed from a prediction queue that stores predicted address blocks.

Abstract: An annular seal assembly for use in a fluid mover, such as a compressor, having a tangentially-cut ring assembly and a radially-cut ring assembly, each ring assembly having arcuate segments, where each arcuate segment of the tangentially-cut ring assembly has a plurality of passages extending from the outer peripheral face to within at least 1.0 mm of the inner peripheral face, wherein after wearing in of the seal, the passages extend through the tangentially-cut ring assembly for pressure balancing.

Abstract: An annular seal assembly for use in a fluid mover, such as a compressor, having a tangentially-cut ring assembly and a radially-cut ring assembly, each ring assembly having arcuate segments, where each arcuate segment of the tangentially-cut ring assembly has a plurality of passages extending from the outer peripheral face to within at least 1.0 mm of the inner peripheral face, wherein after wearing in of the seal, the passages extend through the tangentially-cut ring assembly for pressure balancing.

Abstract: The techniques described herein provide an instruction fetch and decode unit having an operation cache with low latency in switching between fetching decoded operations from the operation cache and fetching and decoding instructions using a decode unit. This low latency is accomplished through a synchronization mechanism that allows work to flow through both the operation cache path and the instruction cache path until that work is stopped due to needing to wait on output from the opposite path. The existence of decoupling buffers in the operation cache path and the instruction cache path allows work to be held until that work is cleared to proceed. Other improvements, such as a specially configured operation cache tag array that allows for detection of multiple hits in a single cycle, also improve latency by, for example, improving the speed at which entries are consumed from a prediction queue that stores predicted address blocks.

Abstract: A processor uses a token scheme to govern the maximum number of memory access requests each of a set of processor cores can have pending at a northbridge of the processor. To implement the scheme, the northbridge issues a minimum number of tokens to each of the processor cores and keeps a number of tokens in reserve. In response to determining that a given processor core is generating a high level of memory access activity the northbridge issues some of the reserve tokens to the processor core. The processor core returns the reserve tokens to the northbridge in response to determining that it is not likely to continue to generate the high number of memory access requests, so that the reserve tokens are available to issue to another processor core.

Abstract: A processor uses a token scheme to govern the maximum number of memory access requests each of a set of processor cores can have pending at a northbridge of the processor. To implement the scheme, the northbridge issues a minimum number of tokens to each of the processor cores and keeps a number of tokens in reserve. In response to determining that a given processor core is generating a high level of memory access activity the northbridge issues some of the reserve tokens to the processor core. The processor core returns the reserve tokens to the northbridge in response to determining that it is not likely to continue to generate the high number of memory access requests, so that the reserve tokens are available to issue to another processor core.

Abstract: A multiplexer (MUX) circuit with balanced select line loading is provided. The MUX circuit includes a plurality of 2:1 MUX units coupled together in a multistage cascading arrangement, along with a selection module coupled to the MUX units. The MUX units are arranged in an initial MUX stage, at least one intermediate MUX stage coupled to and following the initial MUX stage, and a final MUX stage coupled to and following the at least one intermediate MUX stage. Each MUX unit is controlled with a respective select bit input value provided by the selection module. The selection module controls the operation of the MUX units in the initial MUX stage with a first plurality of different select bits, controls the operation of the MUX units in the at least one intermediate MUX stage with a second plurality of different select bits, and controls the operation of the final MUX stage with a devoted select bit.

Abstract: A first address is received and is used to determine a first address range. The first address range includes a second address range and a third address range. If the first address is in the second address range, a fourth address range is determined. The fourth address range is different from the first address range. Information is retrieved from a memory in response to determining that a second address is in the first address range or the fourth address range. If the first address is in the third address range, a fifth address range is determined. The fifth address range is different from the first address range. Other information is retrieved from the memory in response to determining the second address is in the first address range or the fifth address range.

Abstract: A first address is received and is used to determine a first address range. The first address range includes a second address range and a third address range. If the first address is in the second address range, a fourth address range is determined. The fourth address range is different from the first address range. Information is retrieved from a memory in response to determining that a second address is in the first address range or the fourth address range. If the first address is in the third address range, a fifth address range is determined. The fifth address range is different from the first address range. Other information is retrieved from the memory in response to determining the second address is in the first address range or the fifth address range.

Abstract: Industrial gas customer station components comprising a plurality of cryogenic storage tanks each having top and bottom nozzles in flow communication with first and second tank piping connection points, respectively, disposed at a defined distance apart, thereby providing standardized first and second tank piping connection points, and a plurality of piping skids each comprising first and second pipe sections having first and second ends, the first ends thereof defining first and second piping skid connection points disposed at a defined distance apart, thereby providing standardized first and second piping skid connection points. The defined distances between the respective first and second piping skid connection points and the first and second tank piping connection points are essentially equal.

Abstract: Method of designing a customer station adapted to receive a cryogenic liquid, store the cryogenic liquid, discharge the cryogenic liquid after storage, and either provide the cryogenic liquid as a liquid product to a user or vaporize the cryogenic liquid to provide a gas product to a user. The method comprises selecting design parameters including product type, range of product flow rates, and required pipe diameters and piping types. Standardized piping skids are designed for one or more of the combinations of product type, pipe size, and pipe type. The product requirements of a user are defined, the type of cryogenic liquid storage tank is determined, and a piping skid design for the required service is selected from the standardized piping skid designs. The customer station then is designed using the selected standardized piping skid design and the selected type of cryogenic storage tank.