Abstract: A multiported LAN switch comprised of legacy local area network ports and ATM ports. Each ATM port comprising a hardware forwarding engine for bridging LAN frames from the LAN ports to the ATM port. The hardware forwarding engine converts layer 2 protocols between the dissimilar ports expediently, without requiring intervention by a microprocessor. A substantial performance gain is attained compared to microprocessor controlled format converters. Both LAN emulation and virtual LANs are supported.

Abstract: A multiported LAN switch comprised of legacy local area network ports and ATM ports. Each ATM port comprising a hardware forwarding engine for bridging LAN frames from the LAN ports to the ATM port. The hardware forwarding engine converts layer 2 protocols between the dissimilar ports expediently, without requiring intervention by a microprocessor. A substantial performance gain is attained compared to microprocessor controlled format converters. Both LAN emulation and virtual LANs are supported.

Abstract: A multiported LAN switch comprised of legacy local area network ports and ATM ports. Each ATM port comprising a hardware forwarding engine for bridging LAN frames from the LAN ports to the ATM port. The hardware forwarding engine converts layer 2 protocols between the dissimilar ports expediently, without requiring intervention by a microprocessor. A substantial performance gain is attained compared to microprocessor controlled format converters. Both LAN emulation and virtual LANs are supported.

Abstract: A multiported LAN switch comprised of legacy local area network ports and ATM ports. Each ATM port comprising a hardware forwarding engine for bridging LAN frames from the LAN ports to the ATM port. The hardware forwarding engine converts layer 2 protocols between the dissimilar ports expediently, without requiring intervention by a microprocessor. A substantial performance gain is attained compared to microprocessor controlled format converters. Both LAN emulation and virtual LANs are supported.

Abstract: A multiported LAN switch comprised of legacy local area network ports and ATM ports. Each ATM port comprising a hardware forwarding engine for bridging LAN frames from the LAN ports to the ATM port. The hardware forwarding engine converts layer 2 protocols between the dissimilar ports expediently, without requiring intervention by a microprocessor. A substantial performance gain is attained compared to microprocessor controlled format converters. Both LAN emulation and virtual LANs are supported.

Abstract: A multiported LAN switch comprised of legacy local area network ports and ATM ports. Each ATM port comprising a hardware forwarding engine for bridging LAN frames from the LAN ports to the ATM port. The hardware forwarding engine converts layer 2 protocols between the dissimilar ports expediently, without requiring intervention by a microprocessor. A substantial performance gain is attained compared to microprocessor controlled format converters. Both LAN emulation and virtual LANs are supported.

Abstract: A method and system are provided for enabling simultaneous cut-through and store-and-forward transmission of frames in high speed network devices. A Buffer Parameter Vector chains multiple frame buffers together. Frame Parameter Vectors created for each unique version of a frame are used to manage frames as they flow through the network device. Cut-through/store-and-forward decision logic determines whether frames can be transmitted by cut-through or store-and-forward. Multiple unique frames or copies of a frame that are to be transmitted store-and-forward have their Frame Parameter Vectors chained together by pointers. The cut-through/store-and-forward decision logic steps through the chain of Frame Parameter Vectors resulting in the frames associated with each Frame Parameter Vector being transmitted.

Abstract: A multiported LAN switch comprised of legacy local area network ports and ATM ports. Each ATM port comprising a hardware forwarding engine for bridging LAN frames from the LAN ports to the ATM port. The hardware forwarding engine converts layer 2 protocols between the dissimilar ports expediently, without requiring intervention by a microprocessor. A substantial performance gain is attained compared to microprocessor controlled format converters. Both LAN emulation and virtual LANs are supported.

Abstract: A method and system are provided for traffic shaping and bandwidth scaling in a high speed internetworking device. A slot time wheel mechanism is provided for traffic rate control and a credit/debit mechanism is provided for traffic shaping and scaling. The high speed traffic scaler and shaper incorporates a programmable slot time wheel, a traffic scaler state machine, a traffic shaper parameter table and a traffic scaler processor. The traffic scaler processor incorporates a traffic queue allocation manager, a queue priority arbiter, a port enable selector, a port priority arbiter and a DMA channel arbiter. The traffic queue allocation manager and the queue priority, port priority and DMA channel arbiters are each controlled by a corresponding state machine. The parameters in the traffic shaper parameter table are dynamically updated for each logical queue and are used to enable the credit/debit mechanism.

Abstract: A memory interface for multi-port access to a memory unit, such as a static random-access memory (SRAM) device. The memory interface, which is generally adapted for a local area network (LAN) forwarding engine, provides single port read/write access to SRAM device, and arbitrates requests from the access interfaces to allocate bandwidth of the SRAM device among the requests. One embodiment allocates at least 50% of the bandwidth to a peripheral component interface (PCI) bus target interface and a PCI bus master interface, collectively. The arbitration logic may include a plurality of bandwidth control registers associated with respective access interfaces used to determine a permitted amount of bandwidth that an access interface is to have, wherein a request from an access interface is masked based on a value in its associated bandwidth control register. Arbitration can further allocate bandwidth using time division multiplexing.

Abstract: A method of parsing frame headers for routing data frames within a computer network is disclosed. In accordance with the method and system of the present invention, a data frame is first received from a computer network. A frame header of the data frame is then parsed into multiple test units of identical lengths. A test vector is subsequently assigned to each of the test units, wherein each test vector includes a reference pattern field and an action code pointer field. A number of test blocks are constructed by inserting each of the test vectors into a corresponding slot of various test blocks. Finally, a search tree is constructed by utilizing these various test blocks, and each test block is associated with each other test block via the test vectors contained within.

Abstract: A method for improving the performance of an existing busoriented computer system with minimum or no design change to the existing hardware, bus protocol, or bus operation is disclosed. Specifically, the present invention improves the effective bandwidth of an existing bus architecture by creating multiple physical instantiations of the existing bus and directing traffic onto these different buses based on the type of bus operation being performed. This results in multiple components having the capability to simultaneously perform bus operations, therefore improving the effective bandwidth of the system. This invention also allows the components which are current being utilized in the existing bus architecture to be re-utilized with minimum additional external logic.