Abstract: A digital audio processor (20) for a digital audio receiver (21) having an improved automute sequence is disclosed. The digital audio processor (20) includes automute detection circuitry (42) that monitors the amplitude of digital audio signals before and after the application of digital filters by digital audio processing circuitry (20d). The amplitude of the input signals are compared against a first threshold level, while the amplitude of the output signals are compared against a second threshold level. In response to the amplitude of the input signals for all of the audio channels (44) falling below the first threshold for a selected time period, a gain stage (50) in each channel ramps down the volume to a mute level, and pulse-width-modulation circuitry (54) is disabled. If the output signal amplitude falls below a second threshold for a channel, the pulse-width-modulation circuitry (54) for that channel is disabled.

Abstract: A digital audio processor (20) is disclosed, in which digital filter coefficients associated with a plurality of sampling frequencies are stored in a plurality of coefficient memory banks (55). A controller in the digital audio processor (20) selects one of the coefficient memory banks (55) for use in the digital signal processing channels (44). In a manual mode, this selection is in response to a manual selection entry in a bank control register (41). In an automatic mode, indicated by a specific entry in the bank control register (41), sample rate detector circuitry (54) detects the sampling frequency relative to an external reference, such as a crystal (XTL); the appropriate one of the coefficient memory banks (55) is then selected based on sampling frequency associations stored in rate select register (43) in the controller (40).

Abstract: A digital audio-visual receiver (10) with improved digital control of audio volume is disclosed. Upon receipt of a user volume command, via a front panel (25) or a remote control and infrared receiver (27), sequential logic (36) in a volume command processor (35) in a PWM audio processor (20) of the receiver (10) initiates a timer (38), which measures or counts a selected interval. If additional volume commands are received during the interval, sequential logic (36) resets and restarts the timer (38). Upon the timer (38) interval elapsing without another volume command, the volume command processor (35) generates a ramping volume output signal to reach the volume level of the last received volume command over a selected time duration. Audible artifacts during changes in audio volume are thus avoided.

Abstract: A signal processing apparatus includes: (a) A signal treating unit for effecting signal treating functions to present a treated signal at an output. (b) A clock generator receiving a clock signal and using the clock signal for presenting an internal clock signal for use by the signal treating unit. (c) A clock simulating unit occasionally coupled with at least one of the clock signal and the clock generator provides a simulated clock signal generally similar to the internal clock signal when either of the clock signal or the internal clock signal is interrupted. (d) A control unit coupled with the signal treating unit, at least one of the clock signal input locus and the internal clock generator for selectively coupling one of the internal clock signal and the simulated clock signal for use by the signal treating unit.

Abstract: A multiple-channel audio processor (10) and an associated plurality of power stages (22) in an audio system are disclosed. The audio processor (10) includes a plurality of audio amplifier channels (22), each of which includes a pulse-code-modulation (PCM) to pulse-width-modulation (PWM) conversion function (25), which generates PWM signals for application to the plurality of power stages (22). The audio amplifier channels (20) each also include an interchannel delay function (28) for delaying the PWM edges relative to other channels (20), for reducing noise. The audio amplifier channels (20) each also include delay adjust circuitry (32) for gradually increasing and decreasing the interchannel delay of the channel (20) on startup and shutdown. This permits a single control terminal (VALID) at the processor to globally enable and disable all of the power stages (22).