Abstract: A three-terminal snapback device is utilized with a control circuit to provide a low snapback voltage that is protected from non-ESD voltage spikes and ripples. In response to a fast edge, the control circuit lowers the snapback voltage, unless a status signal indicates that normal operating voltages are present, and raises the snapback voltage a predefined time later. If the fast edge represents an ESD pulse, SCR operation is initiated at the lowered snapback voltage. If the fast edge represents a power on sequence, the maximum voltage is less than the momentarily lowered snapback voltage and therefore insufficient to initiate SCR operation. Further, once normal operating voltages are present, the control circuit continuously maintains the raised snapback voltage so that a non-ESD voltage spike or ripple can not improperly turn on the snapback device.

Abstract: A pad that experiences a high-voltage, high dV/dT signal during normal operation is prevented from falsely triggering by utilizing a bipolar transistor connected to the pad to provide ESD protection, and a MOS transistor connected to the bipolar transistor to turn off the bipolar transistor during normal circuit operation.

Abstract: A bootstrap capacitor low voltage prevention circuit and method to control the same is provided. When a low voltage situation is detected the bootstrap capacitor is charged. An over voltage protection circuit is included that prevents the circuit from staying in an over voltage situation for a long period of time.

Abstract: A DC-to-DC converter which includes a current mode switching controller or regulator chip (which includes an oscillator producing a ramped voltage which periodically increases at a fixed ramp rate), circuitry including a current sense resistor external to the integrated circuit controller, and ramp adjustment circuitry (including at least one element external to the integrated circuit controller) which sets the effective ramp rate of the oscillator's ramped voltage. The external element of the ramp adjustment circuitry can be a resistor or a capacitor, or circuitry comprising both a resistor and capacitor.

Abstract: A method and circuit which employs negative feedback to generate a ramped voltage having well controlled maximum amplitude. In preferred embodiments, the invention is an integrated circuit (or portion of an integrated circuit) which generates a ramped voltage with controlled maximum amplitude in a manner independent of process and temperature variations in implementing and operating the circuit. Preferably, the circuit includes an amplifier having an input coupled to receive a reference signal, an output coupled to ramped voltage generator, and another input coupled to the output of the ramped voltage generator, thus implementing a negative feedback loop in which the amplifier asserts feedback to control the maximum amplitude of the ramped voltage generated by the ramped voltage generator.

Abstract: A circuit having multiple channels for generating multiple ramped voltage signals (preferably of a type useful in an interleaved PWM dc/dc converter) such that each ramped voltage signal has a different phase, and all the ramped voltage signals have a uniform controlled maximum amplitude. The circuit can be implemented as an integrated circuit (or portion of an integrated circuit) which generates the multiple ramped voltage signals with uniform maximum amplitude in a manner independent of process and temperature variations in implementing and operating such integrated circuit.

Abstract: A DC-to-DC converter which includes a switching controller or regulator (implemented as an integrated circuit) and circuitry external to the controller or regulator chip, where the controller or regulator chip includes soft start circuitry but requires no component external thereto (other than the external circuitry present in DC-to-DC converters having no soft start capability) in order to accomplish a soft start. The invention is especially useful where it is impractical or undesirable to implement the controller or regulator chip with a pin dedicated for connection to an external soft start capacitor or other component or circuit for performing a soft start operation.

Abstract: A switching controller or regulator (implemented as an integrated circuit) which is operable in any selected one of multiple two modes, including an oscillator mode in which it generates switch control signals for turning on a power switch in response to internally generated clock pulses, a sync mode in which it generates the switch control signals in response to pulses supplied from external circuitry, and preferably also a shutdown mode in which it consumes little or no power and does not generate switch control signals. In the oscillator and sync modes, the controller or regulator also generates additional control signals for turning off the power switch each time after it is turned on, so as to regulate the duty cycle of the power switch.