Abstract: A balanced-to-unbalanced (balun) transformer may include two metal layers on a substrate, a first winding following a first winding path, and a second winding following a second winding path, where each winding is formed in one or more of the two metal layers. The winding paths may include winding segments each disposed around a central axis of the balun transformer, where connectors join adjacent winding segments such that the winding paths are continuous between ends of the windings. The second winding path may be interwoven with, but independent from, the first winding path to form a resultant pattern that is substantially symmetrical. The second winding may include a number, n, of sub-windings, where n>1 such that a resultant number of winding segments of the second winding is greater than a resultant number of winding segments of the first winding by a factor of n.

Abstract: A balanced-to-unbalanced (balun) transformer may include two metal layers on a substrate, a first winding following a first winding path, and a second winding following a second winding path, where each winding is formed in one or more of the two metal layers. The winding paths may include winding segments each disposed around a central axis of the balun transformer, where connectors join adjacent winding segments such that the winding paths are continuous between ends of the windings. The second winding path may be interwoven with, but independent from, the first winding path to form a resultant pattern that is substantially symmetrical. The second winding may include a number, n, of sub-windings, where n>1 such that a resultant number of winding segments of the second winding is greater than a resultant number of winding segments of the first winding by a factor of n.

Abstract: A reconfigurable wideband analog-to-digital converter (ADC) system comprising a first converter stage including a first sample and hold circuit for sampling an input signal, a first ADC configured to generate a digital representation of the sampled input signal from the first sample and hold circuit, and a first digital-to-analog converter (DAC) responsive to the output of the first ADC and configured to generate an analog representation of the digital representation of the sampled input signal. A control processor is provided and configured to generate a digital control signal. A current control circuit is responsive to the digital control signal for generating an analog current control signal for selectively altering a characteristic of at least one of the first ADC and the first DAC.

Abstract: A reconfigurable wideband analog-to-digital converter (ADC) system comprising a first converter stage including: a first signal path including a first sample and hold circuit responsive to an input signal for sampling the input signal at a first resolution; a second signal path arranged parallel to the first signal path and including a second sample and hold circuit responsive to the input signal for sampling the input signal at a second resolution; and a control circuit arranged in series with the first and second signal paths and configured to isolate one of the first and second signal paths from an output of the control circuit in response to a control signal.

Abstract: A reconfigurable wideband analog-to-digital converter (ADC) system comprising a first converter stage having a first signal path including a first sample and hold circuit for sampling an input signal at a first resolution, and a second signal path responsive to the input signal and arranged in parallel with the first signal path. The second signal path includes a second sample and hold circuit for sampling the input signal at a second resolution. A first ADC is also included for generating a digital representation of the input signal sampled by the first converter stage. A control processor is arranged between outputs of the first and second sample and hold circuits and the input of the ADC for selectively providing the signal sampled by one of the first or second sample and hold circuit to the input of the ADC.

Abstract: A clocking scheme for a reconfigurable wideband analog-to-digital converter (ADC) including a plurality of Delay Locked Loops (DLLs) arranged in parallel. Each DLL is responsive to an input clock signal and configured to selectively generate a plurality of output clock signals for controlling the operation of the ADC.