Abstract: A method for applying stress conditions to integrated circuit device samples during accelerated stress testing may include partitioning each of the integrated circuit device samples into a first region having a first functional element, partitioning each of the integrated circuit device samples into at least one second region having at least one second functional element, applying a first stress condition to the first region having the first element, applying a second stress condition to the at least one second region having the at least one second element, determining a first portion of the integrated circuit device samples that functionally failed based on the first stress condition, and determining a second portion of the integrated circuit device samples that functionally failed based on the second stress condition. An acceleration model parameter is derived based on the determining of the first and second portion of the integrated circuit samples that functionally failed.

Abstract: A method for applying stress conditions to integrated circuit device samples during accelerated stress testing may include partitioning each of the integrated circuit device samples into a first region having a first functional element, partitioning each of the integrated circuit device samples into at least one second region having at least one second functional element, applying a first stress condition to the first region having the first element, applying a second stress condition to the at least one second region having the at least one second element, determining a first portion of the integrated circuit device samples that functionally failed based on the first stress condition, and determining a second portion of the integrated circuit device samples that functionally failed based on the second stress condition. An acceleration model parameter is derived based on the determining of the first and second portion of the integrated circuit samples that functionally failed.

Abstract: A method for applying stress conditions to integrated circuit device samples during accelerated stress testing may include partitioning each of the integrated circuit device samples into a first region having a first functional element, partitioning each of the integrated circuit device samples into at least one second region having at least one second functional element, applying a first stress condition to the first region having the first element, applying a second stress condition to the at least one second region having the at least one second element, determining a first portion of the integrated circuit device samples that functionally failed based on the first stress condition, and determining a second portion of the integrated circuit device samples that functionally failed based on the second stress condition. An acceleration model parameter is derived based on the determining of the first and second portion of the integrated circuit samples that functionally failed.

Abstract: A method for applying stress conditions to integrated circuit device samples during accelerated stress testing may include partitioning each of the integrated circuit device samples into a first region having a first functional element, partitioning each of the integrated circuit device samples into at least one second region having at least one second functional element, applying a first stress condition to the first region having the first element, applying a second stress condition to the at least one second region having the at least one second element, determining a first portion of the integrated circuit device samples that functionally failed based on the first stress condition, and determining a second portion of the integrated circuit device samples that functionally failed based on the second stress condition. An acceleration model parameter is derived based on the determining of the first and second portion of the integrated circuit samples that functionally failed.

Abstract: A method for applying stress conditions to integrated circuit device samples during accelerated stress testing may include partitioning each of the integrated circuit device samples into a first region having a first functional element, partitioning each of the integrated circuit device samples into at least one second region having at least one second functional element, applying a first stress condition to the first region having the first element, applying a second stress condition to the at least one second region having the at least one second element, determining a first portion of the integrated circuit device samples that functionally failed based on the first stress condition, and determining a second portion of the integrated circuit device samples that functionally failed based on the second stress condition. An acceleration model parameter is derived based on the determining of the first and second portion of the integrated circuit samples that functionally failed.

Abstract: Methods and systems optimize power usage in an integrated circuit design by sorting the integrated circuit devices after manufacture into relatively slow integrated circuit devices and relatively fast integrated circuit devices to classify the integrated circuit devices into different voltage bins. The methods and systems establish a bin-specific reliability testing processes for each of the voltage bins and test the integrated circuit devices using a tester. This allows the methods and systems to identify as defective ones of the integrated circuit devices that fail the bin-specific integrated circuit reliability testing processes of a corresponding voltage bin. The methods and systems remove the defective ones of the integrated circuit devices to allow only non-defective integrated circuit devices to remain and supply the non-defective integrated circuit devices to a customer.

Abstract: Disclosed is an integrated circuit (IC) chip with a built-in self-test (BIST) architecture that allows for in the field accelerated stress testing. The IC chip can comprise an embedded processor, which selectively alternates operation of an on-chip test block between a stress mode and a test mode whenever the IC chip is powered-on such that, during the stress mode, the test block operates at a higher voltage level than an on-chip functional block and such that, during the test mode, the test block operates at a same voltage level as the functional block and is subjected to testing. Also disclosed are a system, method and computer program product which access the results of such testing from IC chips in a variety of different types of products in order model IC chip performance degradation and to generate IC chip end of life predictions specific to the different types of products.

Abstract: A method for applying stress conditions to integrated circuit device samples during accelerated stress testing may include partitioning each of the integrated circuit device samples into a first region having a first functional element, partitioning each of the integrated circuit device samples into at least one second region having at least one second functional element, applying a first stress condition to the first region having the first element, applying a second stress condition to the at least one second region having the at least one second element, determining a first portion of the integrated circuit device samples that functionally failed based on the first stress condition, and determining a second portion of the integrated circuit device samples that functionally failed based on the second stress condition. An acceleration model parameter is derived based on the determining of the first and second portion of the integrated circuit samples that functionally failed.

Abstract: Disclosed is an integrated circuit (IC) chip with a built-in self-test (BIST) architecture that allows for in the field accelerated stress testing. The IC chip can comprise an embedded processor, which selectively alternates operation of an on-chip test block between a stress mode and a test mode whenever the IC chip is powered-on such that, during the stress mode, the test block operates at a higher voltage level than an on-chip functional block and such that, during the test mode, the test block operates at a same voltage level as the functional block and is subjected to testing. Also disclosed are a system, method and computer program product which access the results of such testing from IC chips in a variety of different types of products in order model IC chip performance degradation and to generate IC chip end of life predictions specific to the different types of products.

Abstract: Methods and systems optimize power usage in an integrated circuit design by sorting the integrated circuit devices after manufacture into relatively slow integrated circuit devices and relatively fast integrated circuit devices to classify the integrated circuit devices into different voltage bins. The methods and systems establish a bin-specific reliability testing processes for each of the voltage bins and test the integrated circuit devices using a tester. This allows the methods and systems to identify as defective ones of the integrated circuit devices that fail the bin-specific integrated circuit reliability testing processes of a corresponding voltage bin. The methods and systems remove the defective ones of the integrated circuit devices to allow only non-defective integrated circuit devices to remain and supply the non-defective integrated circuit devices to a customer.