Patents by Inventor Douglas S. Search
Douglas S. Search has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8171442Abstract: A method to at least partially isolate a net of a circuit design is provided and includes testing a timing characteristic of a circuit design, identifying from a result of the testing a net of the circuit design to be at least partially isolated from an adjacent net and determining a percentage of the identified net to be partially isolated.Type: GrantFiled: September 11, 2009Date of Patent: May 1, 2012Assignee: International Business Machines CorporationInventors: Alexandra Echegaray, Heidi L. Lagares, Douglas S. Search, Stephen Szulewski
-
Patent number: 8141019Abstract: A circuit design process is executed to preserve overall design quality while obtaining quality placements for a full class of pipeline structure signatures. The process employs a method for optimizing pipeline structure placement in a circuit design, by initiating an analysis of pipeline logic structures for correcting poor quality of result (QOR) placements by identifying poor placements caused by placement algorithmic response to degenerate cases and in the process of analysis preserving high quality placements of global placement and timing to preserve preponderant non-degenerate cases in said circuit design. Then employing a plurality of global placement steps, wherein each subsequent placement's QOR is dependent upon the prior placement's quality of result QOR, circuits are identified as being involved in a class of degenerate cases, and circuits having poor placements are removed by stripping them from the global placement solution and also other non-degenerate poor quality placements are corrected.Type: GrantFiled: January 5, 2009Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: James J. Curtin, Douglas S. Search
-
Patent number: 8032851Abstract: A design structure for reducing coupling between wires of an electronic circuit is proposed, wherein sets of nets are classified according to their coupling characteristics, and spacing between wires assigned to the sets of nets is chosen according to the coupling characteristics.Type: GrantFiled: August 28, 2007Date of Patent: October 4, 2011Assignee: International Business Machines CorporationInventors: Moussadek Belaidi, Markus Buehler, James J. Curtin, Adam P. Matheny, Bryan A. Meyer, Douglas S. Search, Dhaval R. Sejpal, Charles Vakirtzis
-
Patent number: 8006208Abstract: A routing method for reducing coupling between wires of an electronic circuit is proposed, wherein sets of nets are classified according to their coupling characteristics, and spacing between wires assigned to the sets of nets is chosen according to the coupling characteristics.Type: GrantFiled: May 18, 2010Date of Patent: August 23, 2011Assignee: International Business Machines CorporationInventors: Moussadek Belaidi, Markus Buehler, James J. Curtin, Adam P. Matheny, Bryan A. Meyer, Douglas S. Search, Dhaval R. Sejpal, Charles Vakirtzis
-
Patent number: 7921398Abstract: A method for determining placement of circuitry during integrated circuit design is presented. The method includes accessing a net list identifying circuitry connections. A plurality of individual net weights are assigned to nets in timing paths within the net list. A composite net weight is determined for said timing paths, the composite net weight being in response to the plurality of individual net weights. Concurrently therewith it is advantageous to utilize our new method of improvements of concurrently proceeding to improve wireability of said design by additional timing optimization and net weight mapping modification steps.Type: GrantFiled: March 13, 2008Date of Patent: April 5, 2011Assignee: International Business Machines CorporationInventors: James J. Curtin, Jose L. Neves, Douglas S. Search
-
Publication number: 20110066989Abstract: A method to at least partially isolate a net of a circuit design is provided and includes testing a timing characteristic of a circuit design, identifying from a result of the testing a net of the circuit design to be at least partially isolated from an adjacent net and determining a percentage of the identified net to be partially isolated.Type: ApplicationFiled: September 11, 2009Publication date: March 17, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alexandra Echegaray, Heidi L. Lagares, Douglas S. Search, Stephen Szulewski
-
Patent number: 7904861Abstract: A method, system, and computer program product for coupled noise timing violation avoidance in detailed routing of an integrated circuit design are provided. The method includes calculating a noise induced timing violation sensitivity (NITVS) metric for nets in the integrated circuit design as a measure of sensitivity to a timing violation relative to a coupled noise delay adder, prioritizing routing isolation as a function of the NITVS metric for each of the nets to avoid coupled noise timing violations, and outputting the routing isolation priority.Type: GrantFiled: June 13, 2007Date of Patent: March 8, 2011Assignee: International Business Machines CorporationInventors: Markus Buehler, Moussadek Belaidi, James J. Curtin, Adam P. Matheny, Bryan A. Meyer, Douglas S. Search, Dhaval R. Sejpal, Charles Vakirtzis
-
Patent number: 7823108Abstract: An integrated circuit chip is made using Genie, a described computer chip design tool which can analyze the data contained within an entire endpoint report, compute relationships between paths based on shared segments, and display this information graphically to the designer. Specifically, Genie groups failing paths into Timing Islands. A timing island is a group of paths which contain at least one shared segment. The most frequently shared segment is sifted to the top of the priority list for each island, and is labeled as the Hub. Thinking of timing islands as a tree, the hub of the island would be the trunk. If you chop the tree down by the trunk, all of the branches, limbs and twigs will fall down too. This is analogous to fixing the timing failures in the hub, and the fix trickling out to each of the segments that dangle off the hub.Type: GrantFiled: November 5, 2007Date of Patent: October 26, 2010Assignee: International Business Machines CorporationInventors: James J. Curtin, Michael J. Cadigan, Jr., Edward J. Hughes, Kevin M. Mcllvain, Jose L. Neves, Ray Raphy, Douglas S. Search
-
Patent number: 7810062Abstract: A method for eliminating negative slack in a netlist representing a chip design uses a contrived timing environment to overlay information onto the design environment during logic and physical synthesis phase. The overlaid timing information determines which netlist transformation provides a maximum leverage for the negative slack elimination and a way for creating a dynamic transformation recipe tuned for each design. The method further provides upper bounds on the negative slack elimination to prevent the netlist transforms from being applied to situations exceeding the capabilities for improving the design.Type: GrantFiled: September 11, 2007Date of Patent: October 5, 2010Assignee: International Business Machines CorporationInventors: James J. Curtin, William E. Dougherty, Jr., Jose L. Neves, Douglas S. Search
-
Publication number: 20100223588Abstract: A routing method for reducing coupling between wires of an electronic circuit is proposed, wherein sets of nets are classified according to their coupling characteristics, and spacing between wires assigned to the sets of nets is chosen according to the coupling characteristics.Type: ApplicationFiled: May 18, 2010Publication date: September 2, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Moussadek Belaidi, Markus Buehler, James J. Curtin, Adam P. Matheny, Bryan A. Meyer, Douglas S. Search, Dhaval R. Sejpal, Charles Vakirtzis
-
Publication number: 20090106711Abstract: Using a computer and storage, a circuit design process is executed to preserve overall design quality while obtaining quality placements for a full class of pipeline structure signatures. These signatures include classic latch to latch pipelines, as well as a variety of latch to latch and mixed logic pipelines. The process employs a method for optimizing pipeline structure placement in a circuit design, by initiating an analysis of pipeline logic structures for correcting poor quality of result (QOR) placements by identifying poor placements caused by placement algorithmic response to degenerate cases and in the process of analysis preserving high quality placements of global placement and timing to preserve preponderant non-degenerate cases in said circuit design.Type: ApplicationFiled: January 5, 2009Publication date: April 23, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James J. Curtin, Douglas S. Search
-
Publication number: 20090070715Abstract: A method for eliminating negative slack in a netlist representing a chip design uses a contrived timing environment to overlay information onto the design environment during logic and physical synthesis phase. The overlaid timing information determines which netlist transformation provides a maximum leverage for the negative slack elimination and a way for creating a dynamic transformation recipe tuned for each design. The method further provides upper bounds on the negative slack elimination to prevent the netlist transforms from being applied to situations exceeding the capabilities for improving the design.Type: ApplicationFiled: September 11, 2007Publication date: March 12, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James J. Curtin, William E. Dougherty, JR., Jose L. Neves, Douglas S. Search
-
Patent number: 7496866Abstract: Using a computer and storage, a circuit design process is executed to preserve overall design quality while obtaining quality placements for a full class of pipeline structure signatures. These signatures include classic latch to latch pipelines, as well as a variety of latch to latch and mixed logic pipelines. The process employs a method for optimizing pipeline structure placement in a circuit design, by initiating an analysis of pipeline logic structures for correcting poor quality of result (QOR) placements by identifying poor placements caused by placement algorithmic response to degenerate cases and in the process of analysis preserving high quality placements of global placement and timing to preserve preponderant non-degenerate cases in said circuit design.Type: GrantFiled: June 22, 2006Date of Patent: February 24, 2009Assignee: International Business Machines CorporationInventors: James J. Curtin, Douglas S. Search
-
Publication number: 20080313588Abstract: A method, system, and computer program product for coupled noise timing violation avoidance in detailed routing of an integrated circuit design are provided. The method includes calculating a noise induced timing violation sensitivity (NITVS) metric for nets in the integrated circuit design as a measure of sensitivity to a timing violation relative to a coupled noise delay adder, prioritizing routing isolation as a function of the NITVS metric for each of the nets to avoid coupled noise timing violations, and outputting the routing isolation priority.Type: ApplicationFiled: June 13, 2007Publication date: December 18, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Markus Buehler, Moussadek Belaidi, James J. Curtin, Adam P. Matheny, Bryan A. Meyer, Douglas S. Search, Dhaval R. Sejpal, Charles Vakirtzis
-
Publication number: 20080184186Abstract: A design structure for reducing coupling between wires of an electronic circuit is proposed, wherein sets of nets are classified according to their coupling characteristics, and spacing between wires assigned to the sets of nets is chosen according to the coupling characteristics.Type: ApplicationFiled: August 28, 2007Publication date: July 31, 2008Inventors: Moussadek Belaidi, Markus Buehler, James J. Curtin, Adam P. Matheny, Bryan A. Meyer, Douglas S. Search, Dhaval R. Sejpal, Charles Vakirtzis
-
Publication number: 20080163149Abstract: A method for determining placement of circuitry during integrated circuit design is presented. The method includes accessing a net list identifying circuitry connections. A plurality of individual net weights are assigned to nets in timing paths within the net list. A composite net weight is determined for said timing paths, the composite net weight being in response to the plurality of individual net weights. Concurrently therewith it is advantageous to utilize our new method of improvements of concurrently proceeding to improve wireability of said design by additional timing optimization and net weight mapping modification steps.Type: ApplicationFiled: March 13, 2008Publication date: July 3, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James J. Curtin, Jose L. Neves, Douglas S. Search
-
Publication number: 20080148213Abstract: A routing method for reducing coupling between wires of an electronic circuit is proposed, wherein sets of nets are classified according to their coupling characteristics, and spacing between wires assigned to the sets of nets is chosen according to the coupling characteristics.Type: ApplicationFiled: August 27, 2007Publication date: June 19, 2008Inventors: Moussadek Belaidi, Markus Buehler, James J. Curtin, Adam P. Matheny, Bryan A. Meyer, Douglas S. Search, Dhaval R. Sejpal, Charles Vakirtzis
-
Patent number: 7376924Abstract: A method for determining placement of circuitry during integrated circuit design is presented. The method includes accessing a net list identifying circuitry connections. A plurality of individual net weights are assigned to nets in timing paths within the net list. A composite net weight is determined for said timing paths, the composite net weight being in response to the plurality of individual net weights. Concurrently therewith it is advantageous to utilize our new method of improvements of concurrently proceeding to improve wireability of said design by additional timing optimization and net weight mapping modification steps.Type: GrantFiled: July 13, 2005Date of Patent: May 20, 2008Assignee: International Business Machines CorporationInventors: James J. Curtin, Jose L. Neves, Douglas S. Search
-
Patent number: 7356793Abstract: Genie is a described computer chip design tool which can analyze the data contained within an entire endpoint report, compute relationships between paths based on shared segments, and display this information graphically to the designer. Specifically, Genie groups failing paths into Timing Islands. A timing island is a group of paths which contain at least one shared segment. The most frequently shared segment is sifted to the top of the priority list for each island, and is labeled as the Hub. Thinking of timing islands as a tree, the hub of the island would be the trunk. If you chop the tree down by the trunk, all of the branches, limbs and twigs will fall down too. This is analogous to fixing the timing failures in the hub, and the fix trickling out to each of the segments that dangle off the hub.Type: GrantFiled: May 16, 2005Date of Patent: April 8, 2008Assignee: International Business Machines CorporationInventors: James J. Curtin, Michael J. Cadigan, Jr., Edward J. Hughes, Kevin M. McIlvain, Jose L. Neves, Ray Raphy, Douglas S. Search
-
Publication number: 20070300192Abstract: Using a computer and storage, a circuit design process is executed to preserve overall design quality while obtaining quality placements for a full class of pipeline structure signatures. These signatures include classic latch to latch pipelines, as well as a variety of latch to latch and mixed logic pipelines. The process employs a method for optimizing pipeline structure placement in a circuit design, by initiating an analysis of pipeline logic structures for correcting poor quality of result (QOR) placements by identifying poor placements caused by placement algorithmic response to degenerate cases and in the process of analysis preserving high quality placements of global placement and timing to preserve preponderant non-degenerate cases in said circuit design.Type: ApplicationFiled: June 22, 2006Publication date: December 27, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James J. Curtin, Douglas S. Search