Patents by Inventor Douglas S. Smith

Douglas S. Smith has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240124582
    Abstract: The present invention is directed to the anti-LAG-3 antibodies, LAG-3 mAb 1, LAG-3 mAb 2, LAG-3 mAb 4, LAG-3 mAb 5, and LAG-3 mAb 6, and to humanized and chimeric versions of such antibodies. The invention additionally pertains to LAG-3-binding molecules that comprise LAG-3 binding fragments of such anti-LAG-3 antibodies, immunocongugates, and to bispecific molecules, including diabodies, BiTEs, bispecific antibodies, etc., that comprise (i) such LAG-3-binding fragments, and (ii) a domain capable of binding an epitope of a molecule involved in regulating an immune check point present on the surface of an immune cells. The present invention also pertains to methods of detecting LAG-3, as well as methods of using molecules that bind LAG-3 for stimulating immune responses.
    Type: Application
    Filed: November 21, 2023
    Publication date: April 18, 2024
    Inventors: Ross LA MOTTE-MOHS, Kalpana SHAH, Douglas H. SMITH, Leslie S. JOHNSON, Paul A. MOORE, Ezio BONVINI, Scott KOENIG
  • Patent number: 11953706
    Abstract: Wavelength-selective films are visibly apparent under the selective wavelength. Wavelength-selective films typically reflect off axis the selected wavelength and therefore can provide high-contrast against a background when applied in a pattern on a substrate. However, it is difficult to apply unique patterned embedded images from film. Disclosed is a cost-effective method and construction of a patterned wavelength-selective image to a substrate. In the disclosed wavelength-selective image, wavelength-selective film particles are applied to an adhesive pattern to create the wavelength-selective image.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: April 9, 2024
    Assignee: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: Kui Chen-Ho, Kenneth L. Smith, Douglas S. Dunn, Tien Yi T. H. Whiting, John A. Wheatley, Bryan T. Whiting, Taylor J. Kobe, Anthony F. Schultz, Duane D. Fansler, Jonah Shaver
  • Patent number: 11920833
    Abstract: A heating, ventilating, and air conditioning (HVAC) system includes a refrigerant loop having a compressor, where the compressor is configured to circulate a refrigerant through the refrigerant loop, a first heat exchanger disposed along the refrigerant loop, where the first heat exchanger is configured to place the refrigerant in a first heat exchange relationship with a working fluid, and an air handling unit having a second heat exchanger, where the second heat exchanger is configured to place the working fluid in a second heat exchange relationship with an airflow, and where the air handling unit is isolated from the first heat exchanger to reduce or eliminate mixing of refrigerant with the airflow.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: March 5, 2024
    Assignee: Johnson Controls Tyco IP Holdings LLP
    Inventors: Ryan L. Snider, Rajiv K. Karkhanis, Chandra S. Yelamanchili, Curtis W. Caskey, Kevin R. Stockton, Nicholas P. Mislak, Douglas A. Kester, Troy E. Smith
  • Patent number: 8912935
    Abstract: A digital input includes a galvanically isolated section having an integrating capacitor coupled to a high voltage signal input by at least one current-limiting resistor, a relaxation oscillator coupled across the integrating capacitor, and an electronic switch controlled by the relaxation oscillator. An optical isolator has an input side and an output side, wherein the input side is coupled across the integrating capacitor by the switch, and a low voltage section includes a decoder having an input coupled to the output side of the optical isolator and having a low voltage signal output.
    Type: Grant
    Filed: December 26, 2013
    Date of Patent: December 16, 2014
    Assignee: Maxim Integrated Products, Inc.
    Inventor: Douglas S. Smith
  • Patent number: 8193495
    Abstract: A system and apparatus that removes and collects non-functional wire assemblies from dicorotron units is described. It has a removal tool with flexible levers mounted on the top of a storage box. The removal tool has an open top and bottom, the open bottom is aligned with an opening in the top of the box to permit a dislodged anchor and wire assembly to fall therethrough.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: June 5, 2012
    Assignee: Xerox Corporation
    Inventors: Bruce J. Parks, Jamie S. Clayfield, Douglas S Smith, James D. Walsh, Eliud Robles Flores, Gerald F. Daloia
  • Publication number: 20080307638
    Abstract: A system and apparatus that removes and collects non-functional wire assemblies from dicorotron units is described. It has a removal tool with flexible levers mounted on the top of a storage box. The removal tool has an open top and bottom, the open bottom is aligned with an opening in the top of the box to permit a dislodged anchor and wire assembly to fall therethrough.
    Type: Application
    Filed: August 28, 2008
    Publication date: December 18, 2008
    Applicant: XEROX CORPORATION
    Inventors: Bruce J. Parks, Jamie S. Clayfield, Douglas S. Smith, James D. Walsh, Eliud Robles Flores, Gerald F. Daloia
  • Patent number: 7432504
    Abstract: A system and apparatus that removes and collects non-functional wire assemblies from dicorotron units is described. It has a removal tool mounted on the top of a storage box. The removal tool has an open top and bottom, the open bottom is aligned with an opening in the top of the box to permit a dislodged wire assembly to fall therethrough.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: October 7, 2008
    Assignee: Xerox Corporation
    Inventors: Bruce J. Parks, Jamie S. Clayfield, Douglas S. Smith, James D. Walsh, Eliud Robles Flores, Gerald F. Daloia
  • Patent number: 7430259
    Abstract: A method for communicating data over a serial interface between a master device and at least one slave device is disclosed. A master device generates a preamble that is attached to a data block for transmission over the serial interface between a master device and at least one slave device. Upon receipt of the control word at the at least one slave device, the preamble is detected by the slave device. Upon detection of the preamble, the slave device is enabled to respond to information within the control word as appropriate.
    Type: Grant
    Filed: May 21, 2004
    Date of Patent: September 30, 2008
    Assignee: Intersil Americas Inc.
    Inventors: Brian North, Douglas S. Smith
  • Patent number: 7420169
    Abstract: Electrostatic printing processes utilize corona-charging units. When those units wear out or become faulty, they need to be replaced. This embodiment provides a tool that can be used to remove a faulty electrode wire assembly from the unit. This same tool when loaded with a new wire assembly can insert a new wire assembly into the emptied corona charging unit, sometimes referred to as a dicorotron unit. The tool, therefore, is used both to remove or insert a wire assembly from or into a dicorotron unit.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: September 2, 2008
    Assignee: Xerox Corporation
    Inventors: Bruce J. Parks, Jamie S. Clayfield, Douglas S. Smith, James D. Walsh, Eliud Robles Flores, Gerald F. Daloia
  • Patent number: 7212221
    Abstract: Raster Output Scanner (ROS) shutter system capable of blocking and unblocking harmful radiation selectably, semi-automatically or automatically. The system and uses thereof can be applied to various fields including scanners and printers.
    Type: Grant
    Filed: November 17, 2004
    Date of Patent: May 1, 2007
    Assignee: Xerox Corporation
    Inventors: James D. Walsh, Douglas S. Smith
  • Patent number: 5469104
    Abstract: An active folded cascode includes an amplifier transistor and a source follower transistor configured as a folded cascode with the drain of the amplifier transistor and the source of the follower transistor connected to form a gain node. A feedback transistor has its gate and drain connected to the source and gate of the follower transistor while bias current provided to the drain of the feedback transistor by a current source maintains the gain node at a fixed voltage with respect to a reference voltage. Coupling of the voltage at the gain node to the gate of the source follower transistor by the feedback transistor reduces the effective source impedance of the source follower transistor, providing improved gain and bandwidth properties for the active folded cascode circuit.
    Type: Grant
    Filed: March 28, 1994
    Date of Patent: November 21, 1995
    Assignee: Elantec, Inc.
    Inventors: Douglas S. Smith, Edward C. Bee
  • Patent number: 5101126
    Abstract: A wide dynamic range transconductance stage has two branches, each branch being composed of a plurality of transconductance circuit paths. Each circuit path has a greater transconductance than the other circuit paths for its branch within a respective sub-range of the input signal range for the stage as a whole, with each path dominating the other paths for its branch within its respective sub-range. The overall bandwidth for the stage, its g.sub.m, its noise characteristics and its input voltage range are enhanced as a result. Bandwidth and slew rate may be independently optimized by the designer. Two paths are used for each branch in the preferred embodiment, with one path consisting of a bipolar transistor and the other path either a field effect transistor or a resistor degenerated bipolar transistor. Multiple paths may be used based on the same principle.
    Type: Grant
    Filed: October 15, 1990
    Date of Patent: March 31, 1992
    Assignee: Analog Devices, Inc.
    Inventors: James R. Butler, Douglas S. Smith
  • Patent number: 5077494
    Abstract: A first Schottky diode is connected between the source of a first enhancement JFET and a low voltage line. The drain of the first enhancement JFET is connected through a first active load current source to a high voltage line, and also through a second Schottky diode and a second active load current source to the low voltage line. The first Schottky diode produces a voltage drop which maintains the source of the first enhancement JFET positive with respect to the low voltage line. The second Schottky diode produces a voltage drop complementary to that of the first Schottky diode, which causes the circuit to produce an output voltage across the second current source having a logically low level close to that of the low voltage line.
    Type: Grant
    Filed: August 21, 1989
    Date of Patent: December 31, 1991
    Assignee: Analog Devices, Inc.
    Inventors: Derek F. Bowers, Douglas S. Smith
  • Patent number: 5058745
    Abstract: A package assembly and method of loading and unloading said package assembly is disclosed. The package assembly of the present invention includes moving parts to make the loading and unloading steps of a relatively delicate instrument of substantial weight easier and safe. The basic package assembly includes four component parts: an outer carton 10, an inner carton 12, a blocking panel 14, and top tray 16. In several of the embodiments, the top tray 16 is combined as a single unit with either the blocking panel 14 or the inner carton 12, thus reducing the parts count to three. In the unloading of the instrument, blocking panel 14 and tray 16 are first removed, outer carton 10 is rotated about one of its lower edges 30 to bring side 31 to rest on the floor. During the rotation of outer carton 10, inner carton 12 slides within outer carton 10 to bring the bottom of the enclosed instrument to rest on its bottom surface within the outer carton 10 allowing its easy removal by sliding it from the packaging.
    Type: Grant
    Filed: May 1, 1990
    Date of Patent: October 22, 1991
    Assignee: Hewlett-Packard Company
    Inventors: Gary J. Warner, Douglas S. Smith
  • Patent number: 5055723
    Abstract: An analog switching circuit may be implemented with MESFETs without forward biasing the switching device, and is applicable to JFET switches in general. Switching currents are provided from a nominal input line which closely tracks the true analog input voltage, but is segregated therefrom. A current supply fed from the nominal input line provides transient charging current to the gate of the switching transistor during the switching transition from OFF to ON states. Voltage setting devices hold the gate and source of the enhancement-mode current supply at approximately the nominal supply voltage level when the switching transistor is ON, while a control section holds the gate and source of the current supply device at a negative reference voltage level when the switching transistor is OFF. In either case, the current supply device is inhibited from delivering gate current to the switching transistor during steady state operation.
    Type: Grant
    Filed: February 28, 1989
    Date of Patent: October 8, 1991
    Assignee: Precision Monolithics, Inc.
    Inventors: Derek F. Bowers, Douglas S. Smith
  • Patent number: 5053653
    Abstract: An analog switching circuit may be implemented with MESFETs without forward biasing the switching device, and is applicable to JFET switches in general. Switching currents are provided from the nominal input line which closely tracks the true analog input voltage, but is segregated therefrom. A current supply fed from the nominal input line provides transient charging current to the gate of the switching transistor during the switching transition from OFF to ON states. Voltage setting devices hold the gate and source of the enhancement-mode current supply at approximately the nominal supply voltage level when the switching transistor is ON, while a control section holds the gate and source of the current supply device at a negative reference voltage level when the switching transistor is OFF. In either case, the current supply device is inhibited from delivering gate current to the switching transistor during steady state operation.
    Type: Grant
    Filed: February 8, 1991
    Date of Patent: October 1, 1991
    Assignee: Analog Devices, Inc.
    Inventors: Derek F. Bowers, Douglas S. Smith
  • Patent number: 4933572
    Abstract: A voltage reference circuit is described which is capable of providing either an internally generated voltage having a trimming capability, or an externally generated voltage, with the use of only two pins. The internal voltage is connected through an interrupt circuit to an input/output terminal, which can also receive an externally generated voltage. A trimming terminal is used to apply trimming voltage signals to adjust the internally generated voltage. To convert from the internal to the external voltage source, an interrupt voltage is applied to the trimming terminal which is outside of the normal trimming voltage range. This interrupt voltage actuates an interrupt circuit to interrupt the connection between the internal voltage source and input/output terminal, leaving the output terminal available for the external voltage source.
    Type: Grant
    Filed: October 5, 1989
    Date of Patent: June 12, 1990
    Assignee: Precision Monolithics, Inc.
    Inventors: Douglas S. Smith, Derek F. Bowers