Abstract: A printed circuit board (PCB), including: a ground reference layer; a pre-impregnated (pre-preg) layer having a surface; a first transmission line positioned on the surface; a second transmission line positioned on the surface spaced-apart from the first transmission line a first distance; and a solder mask layer positioned on the surface of the pre-preg layer and surrounding the first transmission line and the second transmission line, the solder mask layer having a thickness and a dielectric constant, wherein the thickness of the solder mask layer and a value of the dielectric constant of the solder mask layer cause convergence of electric fields associated with the first transmission line to be within a second distance from the first transmission line.

Abstract: A printed circuit board (PCB), including: a ground reference layer; a pre-impregnated (pre-preg) layer having a surface; a first transmission line positioned on the surface; a second transmission line positioned on the surface spaced-apart from the first transmission line a first distance; and a solder mask layer positioned on the surface of the pre-preg layer and surrounding the first transmission line and the second transmission line, the solder mask layer having a thickness and a dielectric constant, wherein the thickness of the solder mask layer and a value of the dielectric constant of the solder mask layer cause convergence of electric fields associated with the first transmission line to be within a second distance from the first transmission line.

Abstract: An information handling system includes a control processing unit (CPU) including a dual in-line memory module (DIMM) controller and hosting a basic input output system (BIOS). A first and a second set of DIMMs are connected to the CPU through the DIMM controller and by a first communication channel and a second communication channel, respectively. Each DIMM in the first and second set of DIMMs may be configured by the BIOS to include a unique data bus IO voltage (Vddq) setting for bidirectional communications with the CPU.

Abstract: An information handling system includes a control processing unit (CPU) including a dual in-line memory module (DIMM) controller and hosting a basic input output system (BIOS). A first and a second set of DIMMs are connected to the CPU through the DIMM controller and by a first communication channel and a second communication channel, respectively. Each DIMM in the first and second set of DIMMs may be configured by the BIOS to include a unique data bus IO voltage (Vddq) setting for bidirectional communications with the CPU.

Abstract: A method includes modeling a design of a memory channel to provide a plurality of transfer functions associated with the design and multiplying an input spectrum with each of the transfer functions to provide a plurality of results. The method further includes summing the results to provide an output spectrum for the design, performing an inverse Fast Fourier Transform (FFT) on the output spectrum to provide an output signal for the design, and determining a bit error rate (BER) for the design based on the output signal.

Abstract: A circuit board includes first and second lines of surface mount pads, and a trace. The surface mount pads within the first line extend from a first edge of the circuit board toward a second edge of the circuit board. The surface mount pads within the second line extend from the first edge of the circuit board toward the second edge of the circuit board, and the surface mount pads within the second line are further from a third edge of the circuit board as compared to the surface mount pads within the first line. The trace is located on a top surface of the circuit board, and extends from the third edge to a fourth edge of the circuit board. The spacing between first adjacent surface mount pads within the first line enables the trace to be routed between the first adjacent surface mount pads with less crosstalk between signals on the trace and signals on the surface mount pads within the first line.

Abstract: A circuit board includes first and second lines of surface mount pads, and a trace. The surface mount pads within the first line extend from a first edge of the circuit board toward a second edge of the circuit board. The surface mount pads within the second line extend from the first edge of the circuit board toward the second edge of the circuit board, and the surface mount pads within the second line are further from a third edge of the circuit board as compared to the surface mount pads within the first line. The trace is located on a top surface of the circuit board, and extends from the third edge to a fourth edge of the circuit board. The spacing between first adjacent surface mount pads within the first line enables the trace to be routed between the first adjacent surface mount pads with less crosstalk between signals on the trace and signals on the surface mount pads within the first line.

Abstract: A circuit board includes first and second lines of surface mount pads, and a trace. The surface mount pads within the first line extend from a first edge of the circuit board toward a second edge of the circuit board. The surface mount pads within the second line extend from the first edge of the circuit board toward the second edge of the circuit board, and the surface mount pads within the second line are further from a third edge of the circuit board as compared to the surface mount pads within the first line. The trace is located on a top surface of the circuit board, and extends from the third edge to a fourth edge of the circuit board. The spacing between first adjacent surface mount pads within the first line enables the trace to be routed between the first adjacent surface mount pads with less crosstalk between signals on the trace and signals on the surface mount pads within the first line.

Abstract: A method includes modeling a design of a memory channel to provide a plurality of transfer functions associated with the design, multiplying an input spectrum with each of the transfer functions to provide a plurality of results, summing the results to provide an output spectrum for the design, performing an inverse Fast Fourier Transform (FFT) on the output spectrum to provide an output signal for the design, and determining a bit error rate (BER) for the design based on the output signal.

Abstract: In accordance with embodiments of the present disclosure, a system may include a driver, a plurality of drops, and a plurality of transmission lines, including one transmission line between the driver and one of the plurality of drops and one transmission line between successive adjacent drops. Each particular transmission line of the plurality of transmission lines may be manufactured to have a desired impedance based on a corresponding effective impedance as seen at a drop located on an end of the particular transmission line furthest from the driver in a direction away from the driver.

Abstract: In accordance with embodiments of the present disclosure, a system may include a driver, a plurality of drops, and a plurality of transmission lines, including one transmission line between the driver and one of the plurality of drops and one transmission line between successive adjacent drops. Each particular transmission line of the plurality of transmission lines may be manufactured to have a desired impedance based on a corresponding effective impedance as seen at a drop located on an end of the particular transmission line furthest from the driver in a direction away from the driver.