Abstract: One disclosed embodiment may comprise a design method for a dynamic circuit system. The method may include providing a design for a single stage network comprising a pull-down network that is configured to perform a desired logic function according to a plurality of inputs. The method may also include designing a multi-stage network that includes at least two stages, each of the at least two stages including a pull-down network that receives a respective portion of the plurality of inputs and each of the at least two stages cooperating to perform the desired logic function.

Abstract: A processor purging system comprising a translation lookaside buffer (TLB) having a plurality of translation pairs, at least one memory cache, and logic configured to detect whether at least one of the translation pairs corresponds to a purge signal. The logic is further configured to assert a purge detection signal indicative of whether at least one translation pair corresponds to the purge signal and to determine, based upon the purge detection signal, whether to search the memory cache for a translation pair corresponding to the purge signal.

Abstract: A device testing system that has automated test equipment (ATE), which interfaces to a device under test (DUT). The device testing system selects a test set of data including a plurality of test pairs, indicative of DUT parameter values. The system, selects a subset of the plurality of test pairs from the test set of data tests the DUT via the ATE with a portion of the selected subset based upon the test results of at least one of the test pairs.