Abstract: Systems are provided where a chassis houses an Information Handling System (IHS). The chassis includes a motherboard with one or more CPUs configured to operate as a root complex for a PCIe switch fabric that includes a plurality of PCIe devices of the IHS. The chassis also includes an I/O module providing I/O capabilities for the motherboard. The I/O module includes a network controller configured to allocate network bandwidth for use by a hardware accelerator sled installed in the chassis, unless an integrated network controller is detected as a component of a hardware accelerator baseboard installed in the hardware accelerator sled. The I/O module also includes a PCI switch configured to operate with the CPUs as the root complex of the PCIe switch fabric and further configured to operate with the hardware accelerator baseboard as the root complex of the PCIe switch fabric.

Abstract: Systems are provided where a chassis houses an Information Handling System (IHS). The chassis includes a motherboard with one or more CPUs configured to operate as a root complex for a PCIe switch fabric that includes a plurality of PCIe devices of the IHS. The chassis also includes an I/O module providing I/O capabilities for the motherboard. The I/O module includes a network controller configured to allocate network bandwidth for use by a hardware accelerator sled installed in the chassis, unless an integrated network controller is detected as a component of a hardware accelerator baseboard installed in the hardware accelerator sled. The I/O module also includes a PCI switch configured to operate with the CPUs as the root complex of the PCIe switch fabric and further configured to operate with the hardware accelerator baseboard as the root complex of the PCIe switch fabric.

Abstract: Systems provide a chassis housing one or more Information Handling Systems (IHSs). A control layer of the chassis includes a power supply for use both in the control layer of the chassis and in a processing layer of the chassis. The control layer also includes a motherboard with CPUs coupled to the processing layer via a PCIe switch fabric. The processing layer includes one or more replaceable I/O modules installed in a front compartment. The processing layer also includes a hardware accelerator sled installed in a central compartment of the processing layer, where the hardware accelerator sled is replaceable via a rear of the processing layer. A block of cooling fans is installed in a rear compartment of the processing layer, where the fans provide airflow cooling to the I/O modules and hardware accelerator sled installed in the processing layer. In this configuration, cooling requirements are met for the chassis.

Abstract: A computing apparatus including a printed circuit board (PCB) including a first central processing unit (CPU) socket and additional CPU socket(s); a CPU coupled to the first CPU socket; a base interposer coupled to the additional CPU socket(s); and one or more devices connected to the base interposer, wherein the base interposer provides a connection between the CPU and the one or more devices.

Abstract: A computing apparatus including a printed circuit board (PCB) including a first central processing unit (CPU) socket and additional CPU socket(s); a CPU coupled to the first CPU socket; a base interposer coupled to the additional CPU socket(s); and one or more devices connected to the base interposer, wherein the base interposer provides a connection between the CPU and the one or more devices.

Abstract: A method of updating a test description forming part of an automated test. The method includes obtaining a first time value associated with the sending of an instruction contained within the test description from the test computer to the system under test, obtaining a second time value associated with the receiving of an image comprising at least a portion of a GUI output of the system under test at the test computer, and using one or more processor devices to compare the first and second time values to determine timing information and update the test description using the timing information.

Abstract: A method of updating a test description forming part of an automated test. The method includes obtaining a first time value associated with the sending of an instruction contained within the test description from the test computer to the system under test, obtaining a second time value associated with the receiving of an image comprising at least a portion of a GUI output of the system under test at the test computer, and using one or more processor devices to compare the first and second time values to determine timing information and update the test description using the timing information.

Abstract: A mattress is provided with elevated chest support region and an arm well to reduce sleep disturbance in a person in the prone, sublime or side position. Said mattress is further provided with a firm zone at the foot of the mattress to assist persons transitioning onto and off of the mattress. An adjustable cover for said mattress is provided as is an improved method for packaging said mattress and cover.

Abstract: A battery contact cleaning tool which comprises a top portion, including a brush for cleaning the battery contact; a bottom portion for reaming and/or smoothing a battery contact; and an intermediate portion connecting the top portion and bottom portion. The present invention additionally provides for a cap to cover the brush located on the top portion of the battery cleaning tool.