Patents by Inventor Douglas Stuart McPherson
Douglas Stuart McPherson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11561570Abstract: Described are apparatus and methods for low power frequency clock generation and distribution. A device includes a low power generation and distribution circuit configured to generate and distribute a differential 1/N sampling frequency (FS)(FS/N) clock, wherein N is larger or equal to 2, and a differential frequency doubler configured to generate a single-ended multiplied frequency clock from the differential FS/N frequency clock, and convert the single-ended multiplied frequency clock to a differential multiplied frequency clock for use by one or more data processing channels.Type: GrantFiled: December 1, 2020Date of Patent: January 24, 2023Assignee: Ciena CorporationInventors: Mahdi Parvizi, Sadok Aouini, Naim Ben-Hamida, Yuriy Greshishchev, Douglas Stuart McPherson
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Patent number: 11483007Abstract: Described are apparatus and methods to calibrate and align multiple high-speed clock domains. A system includes at least two clock domains, a launch circuit connected to each of the at least two domains, and a calibration circuit. Each clock domain including a resettable device having a local reset retime clock. The launch circuit aligns a reset pulse with the local reset retime clock by using a launch clock from one of the domains, where the reset pulse is incoherent with respect to the domains, adjusts a delay of the launch clock to control a launch time of the reset pulse, and sends the reset pulse based on the delayed launch clock. The calibration circuit samples a local reset retime delayed clock to generate a readback signal. The launch circuit and the calibration circuit iterate through selected delays until safe arrival timing is indicated from each readout.Type: GrantFiled: June 23, 2021Date of Patent: October 25, 2022Assignee: Ciena CorporationInventors: Jerry Yee-Tung Lam, Douglas Stuart McPherson, Robert Gibbins, Naim Ben-Hamida
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Publication number: 20220171425Abstract: Described are apparatus and methods for low power frequency clock generation and distribution. A device includes a low power generation and distribution circuit configured to generate and distribute a differential 1/N sampling frequency (FS)(FS/N) clock, wherein N is larger or equal to 2, and a differential frequency doubler configured to generate a single-ended multiplied frequency clock from the differential FS/N frequency clock, and convert the single-ended multiplied frequency clock to a differential multiplied frequency clock for use by one or more data processing channels.Type: ApplicationFiled: December 1, 2020Publication date: June 2, 2022Applicant: Ciena CorporationInventors: Mahdi Parvizi, Sadok Aouini, Naim Ben-Hamida, Yuriy Greshishchev, Douglas Stuart McPherson
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Patent number: 11245401Abstract: Described are apparatus and methods for high frequency clock generation. A circuit includes a phase frequency detector (PFD) which outputs differential error clocks based on comparison of differential reference clocks and differential feedback clocks, which are at a first frequency. A controlled oscillator (CO) connected to the PFD, which adjusts a frequency of the CO based on the differential error clocks to generate differential clocks at a second frequency, which is a multiple of the first frequency. A quadrature clock generator connected to the CO, which generates differential quadrature clocks at the second frequency from the differential clocks, where the differential feedback clocks are generated from the differential clocks and one pair of the differential quadrature clocks. A frequency doubler which doubles each pair of the differential quadrature clocks and outputs fully differential and balanced clocks at a third frequency for distribution, which is a multiple of the second frequency.Type: GrantFiled: December 16, 2020Date of Patent: February 8, 2022Assignee: Ciena CorporationInventors: Mahdi Parvizi, Sadok Aouini, Naim Ben-Hamida, Yuriy Greshishchev, Douglas Stuart McPherson, Robert Gibbins, Anna Sakharova
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Patent number: 11196534Abstract: Described are apparatus and methods for low power clock generation in multi-channel high speed devices. In implementations, a multi-channel data processing device includes a low frequency clock generation and distribution circuit configured to generate and distribute a 1/N sampling frequency (FS)(FS/N) clock, wherein N is larger or equal to 8, and multiple data processing channels connected to the low frequency generation and distribution circuit. Each data processing channel including input ports associated with different operating frequency clocks, and a channel local clock generation circuit comprising multipliers associated with some of the input ports, each multiplier configured to multiply the FS/N frequency clock to locally generate an operating frequency clock associated with an input port of the input ports.Type: GrantFiled: December 2, 2020Date of Patent: December 7, 2021Assignee: Ciena CorporationInventors: Mahdi Parvizi, Yuriy Greshishchev, Naim Ben-Hamida, Douglas Stuart McPherson
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Publication number: 20210313992Abstract: Described are apparatus and methods for high frequency clock generation. A circuit includes a phase frequency detector (PFD) which outputs differential error clocks based on comparison of differential reference clocks and differential feedback clocks, which are at a first frequency. A controlled oscillator (CO) connected to the PFD, which adjusts a frequency of the CO based on the differential error clocks to generate differential clocks at a second frequency, which is a multiple of the first frequency. A quadrature clock generator connected to the CO, which generates differential quadrature clocks at the second frequency from the differential clocks, where the differential feedback clocks are generated from the differential clocks and one pair of the differential quadrature clocks. A frequency doubler which doubles each pair of the differential quadrature clocks and outputs fully differential and balanced clocks at a third frequency for distribution, which is a multiple of the second frequency.Type: ApplicationFiled: December 16, 2020Publication date: October 7, 2021Applicant: Ciena CorporationInventors: Mahdi Parvizi, Sadok Aouini, Naim Ben-Hamida, Yuriy Greshishchev, Douglas Stuart McPherson, Robert Gibbins, Anna Sakharova
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Patent number: 10903841Abstract: Described are apparatus and methods for high frequency clock generation. A circuit includes a phase frequency detector (PFD) which outputs differential error clocks based on comparison of differential reference clocks and differential feedback clocks, which are at a first frequency. A controlled oscillator (CO) connected to the PFD, which adjusts a frequency of the CO based on the differential error clocks to generate differential clocks at a second frequency, which is a multiple of the first frequency. A quadrature clock generator connected to the CO, which generates differential quadrature clocks at the second frequency from the differential clocks, where the differential feedback clocks are generated from the differential clocks and one pair of the differential quadrature clocks. A frequency doubler which doubles each pair of the differential quadrature clocks and outputs fully differential and balanced clocks at a third frequency for distribution, which is a multiple of the second frequency.Type: GrantFiled: April 3, 2020Date of Patent: January 26, 2021Assignee: Ciena CorporationInventors: Mahdi Parvizi, Sadok Aouini, Naim Ben-Hamida, Yuriy Greshishchev, Douglas Stuart McPherson, Robert Gibbins, Anna Sakharova
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Patent number: 7529329Abstract: A clock and data recovery circuit (CDR) for receiving high-speed digital data, and having an analog phase offset control capability, is improved by providing an adaptive sampling edge position control. A differential circuit samples the raw data signal at three closely spaced sampling points of the eye, and compares advanced and delayed sampled data with the nominal sampled data. If either the advanced or delayed sampled data differ from the nominal sampled data, i.e. if advanced or delayed errors are detected, a shift in the sampling edge position may be required. A logic circuit performs a method determining the occurrence of advanced or delayed errors over progressively longer time intervals, and to adjust the sampling edge position of the CDR by controlling the phase offset.Type: GrantFiled: November 8, 2004Date of Patent: May 5, 2009Assignee: Applied Micro Circuits CorporationInventors: Petre Popescu, Douglas Stuart McPherson, Hai Tran Quoc, Stanislas Wolski
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Patent number: 7321621Abstract: The invention describes a number of differential, balanced high-speed circuits that permit the design of a receiver with Electronic Dispersion Compensation (EDC) on a single semiconductor substrate, including the functions of an analog Fast Forward Equalizer (FFE), a Clock and Data Recovery, a Decision Feedback Equalizer (DFE), enhanced by additional circuits that permit control of the slicing level to compensate for pulse distortion, and control of the phase offset to set the optimal eye sampling time when a distorted signal is received. To provide the utmost speed of operation, all circuits including the phase locked loop, operate as differential circuits which include a number of improvements in the design of the charge pump, the decision feedback equalizer, the slicing level control, and others.Type: GrantFiled: August 12, 2003Date of Patent: January 22, 2008Assignee: Applied Micro Circuits CorporationInventors: Petre Popescu, Douglas Stuart McPherson, Stefan Szilagyi, Quoc Hai Tran, Kathryn Howlett
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Patent number: 7184478Abstract: The invention describes a number of differential, balanced high-speed circuits that permit the design of a receiver with Electronic Dispersion Compensation (EDC) on a single semiconductor substrate, including the functions of an analog Fast Forward Equalizer (FFE), a Clock and Data Recovery, a Decision Feedback Equalizer (DFE), enhanced by additional circuits that permit control of the slicing level to compensate for pulse distortion, and control of the phase offset to set the optimal eye sampling time when a distorted signal is received. To provide the high speed of operation, all circuits including the phase locked loop, operate as differential circuits, which include a number of improvements in the design of the charge pump, the decision feedback equalizer, the slicing level control, and others.Type: GrantFiled: August 12, 2003Date of Patent: February 27, 2007Assignee: Applied Micro Circuits CorporationInventors: Petre Popescu, Quoc Hai Tran, Douglas Stuart McPherson
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Publication number: 20040258183Abstract: The invention describes a number of differential, balanced high-speed circuits that permit the design of a receiver with Electronic Dispersion Compensation (EDC) on a single semiconductor substrate, including the functions of an analog Fast Forward Equalizer (FFE), a Clock and Data Recovery, a Decision Feedback Equalizer (DFE), enhanced by additional circuits that permit control of the slicing level to compensate for pulse distortion, and control of the phase offset to set the optimal eye sampling time when a distorted signal is received. To provide the high speed of operation, all circuits including the phase locked loop, operate as differential circuits, which include a number of improvements in the design of the charge pump, the decision feedback equalizer, the slicing level control, and others.Type: ApplicationFiled: August 12, 2003Publication date: December 23, 2004Inventors: Petre Popescu, Quoc Hai Tran, Douglas Stuart McPherson
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Publication number: 20040258145Abstract: The invention describes a number of differential, balanced high-speed circuits that permit the design of a receiver with Electronic Dispersion Compensation (EDC) on a single semiconductor substrate, including the functions of an analog Fast Forward Equalizer (FFE), a Clock and Data Recovery, a Decision Feedback Equalizer (DFE), enhanced by additional circuits that permit control of the slicing level to compensate for pulse distortion, and control of the phase offset to set the optimal eye sampling time when a distorted signal is received. To provide the utmost speed of operation, all circuits including the phase locked loop, operate as differential circuits which include a number of improvements in the design of the charge pump, the decision feedback equalizer, the slicing level control, and others.Type: ApplicationFiled: August 12, 2003Publication date: December 23, 2004Inventors: Petre Popescu, Douglas Stuart McPherson, Stefan Szilagyi, Quoc Hai Tran, Kathryn Howlett