Abstract: A method of caching data includes: A. mirroring data processed by a first storage processor and a second storage processor between a first memory device of the first storage processor and a second memory device of the second storage processor; B. each of the first storage processor and the second storage processor monitoring an availability of the other of the first storage processor and the second storage processor; C. copying data stored in the first memory device to a third memory device and mirroring data processed by the first storage processor between the first memory device and the third memory device when the second storage processor becomes unavailable to the first storage processor; and D. copying data from the first memory device to the second memory device and mirroring data processed by the first storage processor and the second storage processor between the first memory device and the second memory device when the second storage processor becomes available to the first storage processor.

Abstract: A data storage system includes a first storage processor including a first memory device; a second storage processor including a second memory device; and a third memory device coupled to the first storage processor and the second storage processor. The first and second storage processors are interconnected to enable mirroring of data between the first memory device and the second memory device. During a first mode of operation, data processed by the first storage processor and the second storage processor is mirrored between the first memory device and the second memory device and, during a second mode of operation, data processed by the first storage processor is mirrored from the first memory device to the third memory device.

Abstract: Flow control settings are configured. Credit settings for credit types of input/output interconnect ports are programmed at a low value. The system type of a system containing the input/output interconnect ports is detected. The credit settings are reprogrammed in accordance with the system type.

Abstract: A method and apparatus are provided for assigning/obtaining enclosure identification numbers in a distributed switch storage system. The method takes advantage a network topology wherein one port on the switch is always used as a downstream connection (towards a control station) and one always used as an upstream connection (away from the control station). Using single-hop type packets an assignment arbitration protocol ensures that each enclosure is assigned a unique and predictable Enclosure ID.

Abstract: A data storage system includes storage array and a switch that is configurable to create numerous network topologies within the system and to maintain separate communications paths between different computerized devices or networks and the storage array. For example, a user device and a service device, such as a system diagnosis device, can connect to the storage array through the switch. In order to isolate interaction or communication between the user and service devices, the switch can be logically partitioned into two distinct switches to form two distinct, isolated communications paths between the devices and the storage array. With isolated communications pathways established in the switch, in use, the service device is unable to access the user device coupled to the storage array.

Abstract: A technique controls a network switch having a set of ports. The technique involves configuring the network switch to provide an initial set of communications paths between the ports. The initial set of communications paths defines an initial communications path topology within the network switch. The technique further involves receiving a configuration command which identifies a particular operating mode of the data storage system after configuring the network switch to provide the initial set of communications paths within the network switch. The technique further involves reconfiguring the network switch to provide a new set of communications paths between the ports in response to the configuration command. The new set of communications paths (i) defines a new communications path topology within the network switch, the new communications path topology being different than the initial communications path topology, and (ii) supports the particular operating mode of the data storage system.

Abstract: A technique responds to a storage processor failure. The technique involves performing write-back caching operations using a cache of a first storage processor, and mirroring data from the cache of the first storage processor to a cache of a second storage processor. The technique further involves, after of a failure of the second storage processor in which the second storage processor becomes unavailable, continuing to perform write-back caching operations using the cache of the first storage processor while the second storage processor remains unavailable. A cache controller is capable of being modified so that any write data in the cache of the first storage processor persists if the first storage processor encounters a failure thus preventing loss of the cached write data.

Abstract: A computerized system includes two storage processors having respective local write caches configured to mirror each other. When a first storage processor becomes unavailable and mirroring of the local write caches is prevented, the computerized system continues to attend to write operations from an external host in a write-back manner by caching write data from the write operations in the local write cache of the second storage processor. In response to a failure of the second storage processor, the computerized system preserves the write data within the local write cache of the second storage processor. Then, upon recovery of the second storage processor from the failure, the computerized system continues to attend to further write operations from the external host in the write-back manner by caching additional write data in the local write cache of the second storage processor while the first storage processor remains unavailable.

Abstract: A system having a processor, a printed circuit board, and an adapter board, coupled to the processor through the printed circuit board. The adapter board provides a first signal having a first state when the adapter board is in a proper operating condition and a second state when the adapter board is in an improper condition. The adapter board produces a second signal having the second state for less than a predetermined time when an adapter board requires a reset signal from the processor. The adapter board combines the first signal with the second signal a single signal fed to the processor through the printed circuit board. When the processor detects that the single signal is in the second state for a time less than the predetermined period of time, the process interprets the single signal as indicating the adapter board requires a reset.

Abstract: System components are managed. Based on a first communication path to a component, first identification information for the component is determined. Based on a second communication path to the component, second identification information for the component is determined. Based on the first identification information and the second identification information, an identity for the component is determined. Based on the identity, a set of tests is performed on the component. Based on the failure rate of the set of tests, it is concluded that another component on the first communication path is faulty.

Abstract: A data storage system includes a storage processor that is configured to perform load and store operations on a storage array on behalf of external devices. The data storage system also includes a controller that isolates communication between the external devices when coupled to the storage array via the storage processor. The controller further maintains a set of registers that store information associated with the data storage system and allows the storage processor to access the register via an I2C bus. The system utilizes an error detection procedure to allow detection of errors in the data transmitted between the controller and the storage processor. During operation, a checksum value is transmitted between the controller and the storage processor using the I2C bus during a register write or read procedure. The controller and the storage processor utilize the checksum value in an error detection procedure to detect the data errors resulting in transmission of the data by the I2C bus.

Abstract: A technique responds to a storage processor failure. The technique involves performing write-back caching operations using a cache of a first storage processor, and mirroring data from the cache of the first storage processor to a cache of a second storage processor. The technique further involves, after of a failure of the second storage processor in which the second storage processor becomes unavailable, continuing to perform write-back caching operations using the cache of the first storage processor while the second storage processor remains unavailable. A cache controller is capable of being modified so that any write data in the cache of the first storage processor persists if the first storage processor encounters a failure thus preventing loss of the cached write data.

Abstract: A computerized system includes two storage processors having respective local write caches configured to mirror each other. When a first storage processor becomes unavailable and mirroring of the local write caches is prevented, the computerized system continues to attend to write operations from an external host in a write-back manner by caching write data from the write operations in the local write cache of the second storage processor. In response to a failure of the second storage processor, the computerized system preserves the write data within the local write cache of the second storage processor. Then, upon recovery of the second storage processor from the failure, the computerized system continues to attend to further write operations from the external host in the write-back manner by caching additional write data in the local write cache of the second storage processor while the first storage processor remains unavailable.

Abstract: Boards in a system are interconnected by a first set of signals including a first control signal and first function signals. Each board in the system includes a second set of signals corresponding to the first set of signals. When the first control signal and a first function signal are asserted, the corresponding second signals of are asserted in response and a function is performed on the boards. But, if any of the second signals are asserted, none of the first signals is asserted in response. Test signals on boards are thereby isolated from test signals coupled to all the boards on the system, so a fault on any signal in any second set of signals will not propagate to the first set of signals.

Abstract: A data storage system includes storage array and a switch that is configurable to create numerous network topologies within the system and to maintain separate communications paths between different computerized devices or networks and the storage array. For example, a user device and a service device, such as a system diagnosis device, can connect to the storage array through the switch. In order to isolate interaction or communication between the user and service devices, the switch can be logically partitioned into two distinct switches to form two distinct, isolated communications paths between the devices and the storage array. With isolated communications pathways established in the switch, in use, the service device is unable to access the user device coupled to the storage array.

Abstract: A hot-pluggable I/O annex module of a storage processor assembly includes interface circuitry providing connections to an optional I/O interface module. The I/O annex module includes redundant cooling fans providing cooling airflow to an I/O annex mounting area, main power conversion circuitry for generating main operating power for the interface circuitry, auxiliary power conversion circuitry for generating auxiliary power, a controller for monitoring and controlling the operation of cooling fans; and monitoring circuitry powered by the auxiliary power for monitoring correct operation of the controller and, upon detecting incorrect operation, disabling the main power conversion circuitry.

Abstract: A data storage system includes a storage processor that is configured to perform load and store operations on a storage array on behalf of external devices. The data storage system also includes a controller that isolates communication between the external devices when coupled to the storage array via the storage processor. The controller further maintains a set of registers that store information associated with the data storage system and allows the storage processor to access the register via an I2C bus. The system utilizes an error detection procedure to allow detection of errors in the data transmitted between the controller and the storage processor. During operation, a checksum value is transmitted between the controller and the storage processor using the I2C bus during a register write or read procedure. The controller and the storage processor utilize the checksum value in an error detection procedure to detect the data errors resulting in transmission of the data by the I2C bus.

Abstract: Communications paths are managed. An error is detected on a first storage processor. It is determined that the error resulted from a peer-to-peer communication from a second storage processor. The error on the first storage processor is handled by taking action short of causing the first storage processor to reset.

Abstract: System availability is managed. It is determined that a data communications link has been established and that the data communications link is less than fully functional. Communication is performed across the data communications link to a device to configure the device for the data communications link. The device is caused to re-establish the data communication link based on the results of the configuring.

Abstract: System components are managed. Based on a first communication path to a component, first identification information for the component is determined. Based on a second communication path to the component, second identification information for the component is determined. Based on the first identification information and the second identification information, an identity for the component is determined. Based on the identity, a set of tests is performed on the component. Based on the failure rate of the set of tests, it is concluded that another component on the first communication path is faulty.