Patents by Inventor Douglas T. Grider
Douglas T. Grider has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230178652Abstract: In some examples, a transistor includes a semiconductor layer having a first conductivity type and a first dopant concentration. A gate dielectric layer is between a gate electrode and the semiconductor layer. A first source/drain region is adjacent a first sidewall of the gate electrode and a second source/drain region is adjacent an opposite second sidewall of the gate electrode, the first and second source/drain regions having an opposite second conductivity type. A well region is located in the semiconductor layer and has the first conductivity type and a greater second dopant concentration. The well region underlies the first sidewall and the semiconductor layer extends to the gate electrode under the second sidewall of the gate electrode.Type: ApplicationFiled: January 30, 2023Publication date: June 8, 2023Inventors: Xiang-Zheng BO, Michelle N. NGUYEN, Douglas T. GRIDER
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Patent number: 11189626Abstract: In accordance with some examples, a system comprises a substrate layer having an outer surface. The system also comprises a plurality of trenches extending from the outer surface into the substrate layer. The system then comprises a plurality of active regions with each active region positioned between a different pair of consecutive trenches of the plurality of trenches. The system also comprises a dielectric layer disposed in each of the plurality of trenches and on each of the plurality of active regions. The system then comprises a gate layer disposed on the dielectric layer and extending at least partially into each of the plurality of trenches.Type: GrantFiled: September 13, 2019Date of Patent: November 30, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Xiang-Zheng Bo, John H. MacPeak, Douglas T. Grider
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Patent number: 11152068Abstract: In some examples, an integrated circuit comprises a first plate, a second plate, and a dielectric layer disposed between the first and second plates, the first and second plates and the dielectric layer forming a vertical capacitor, wherein the first and second plates and the dielectric layer of the vertical capacitor are disposed on an isolation region of the integrated circuit.Type: GrantFiled: March 19, 2020Date of Patent: October 19, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Xiang-Zheng Bo, Patrick R. Smith, Douglas T. Grider
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Publication number: 20210050445Abstract: In some examples, a transistor includes a first well doped with a first-type dopant having a first concentration. The transistor also includes a gate oxide layer on a portion of the first well and a gate layer on the gate oxide layer. The transistor further includes a first segment of a second well doped with the first-type dopant having a second concentration, the first segment underlapping a first portion of the gate layer. The transistor also includes a source region doped with a second-type dopant having a third concentration, the source region in the first segment. The transistor further includes a drain region doped with the second-type dopant having a concentration that is substantially the same as the third concentration.Type: ApplicationFiled: October 14, 2020Publication date: February 18, 2021Inventors: Xiang-Zheng BO, Michelle N. NGUYEN, Douglas T. GRIDER
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Patent number: 10811534Abstract: In some examples, a transistor includes a first well doped with a first-type dopant having a first concentration. The transistor also includes a gate oxide layer on a portion of the first well and a gate layer on the gate oxide layer. The transistor further includes a first segment of a second well doped with the first-type dopant having a second concentration, the first segment underlapping a first portion of the gate layer. The transistor also includes a source region doped with a second-type dopant having a third concentration, the source region in the first segment. The transistor further includes a drain region doped with the second-type dopant having a concentration that is substantially the same as the third concentration.Type: GrantFiled: January 15, 2018Date of Patent: October 20, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Xiang-Zheng Bo, Michelle N. Nguyen, Douglas T. Grider
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Publication number: 20200219566Abstract: In some examples, an integrated circuit comprises a first plate, a second plate, and a dielectric layer disposed between the first and second plates, the first and second plates and the dielectric layer forming a vertical capacitor, wherein the first and second plates and the dielectric layer of the vertical capacitor are disposed on an isolation region of the integrated circuit.Type: ApplicationFiled: March 19, 2020Publication date: July 9, 2020Inventors: Xiang-Zheng BO, Patrick R. SMITH, Douglas T. GRIDER
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Patent number: 10622073Abstract: In some examples, an integrated circuit comprises a first plate, a second plate, and a dielectric layer disposed between the first and second plates, the first and second plates and the dielectric layer forming a vertical capacitor, wherein the first and second plates and the dielectric layer of the vertical capacitor are disposed on an isolation region of the integrated circuit.Type: GrantFiled: May 11, 2018Date of Patent: April 14, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Xiang-Zheng Bo, Patrick R. Smith, Douglas T. Grider
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Publication number: 20200006362Abstract: In accordance with some examples, a system comprises a substrate layer having an outer surface. The system also comprises a plurality of trenches extending from the outer surface into the substrate layer. The system then comprises a plurality of active regions with each active region positioned between a different pair of consecutive trenches of the plurality of trenches. The system also comprises a dielectric layer disposed in each of the plurality of trenches and on each of the plurality of active regions. The system then comprises a floating gate layer disposed on the dielectric layer and extending at least partially into each of the plurality of trenches.Type: ApplicationFiled: September 13, 2019Publication date: January 2, 2020Inventors: Xiang-Zheng BO, John H. MACPEAK, Douglas T. GRIDER
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Publication number: 20190348119Abstract: In some examples, an integrated circuit comprises a first plate, a second plate, and a dielectric layer disposed between the first and second plates, the first and second plates and the dielectric layer forming a vertical capacitor, wherein the first and second plates and the dielectric layer of the vertical capacitor are disposed on an isolation region of the integrated circuit.Type: ApplicationFiled: May 11, 2018Publication date: November 14, 2019Inventors: Xiang-Zheng BO, Patrick R. SMITH, Douglas T. GRIDER
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Patent number: 10446563Abstract: In accordance with some examples, a system comprises a substrate layer having an outer surface. The system also comprises a plurality of trenches extending from the outer surface into the substrate layer. The system then comprises a plurality of active regions with each active region positioned between a different pair of consecutive trenches of the plurality of trenches. The system also comprises a dielectric layer disposed in each of the plurality of trenches and on each of the plurality of active regions. The system then comprises a floating gate layer disposed on the dielectric layer and extending at least partially into each of the plurality of trenches.Type: GrantFiled: April 4, 2018Date of Patent: October 15, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Xiang-Zheng Bo, John H. Macpeak, Douglas T. Grider
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Publication number: 20190312045Abstract: In accordance with some examples, a system comprises a substrate layer having an outer surface. The system also comprises a plurality of trenches extending from the outer surface into the substrate layer. The system then comprises a plurality of active regions with each active region positioned between a different pair of consecutive trenches of the plurality of trenches. The system also comprises a dielectric layer disposed in each of the plurality of trenches and on each of the plurality of active regions. The system then comprises a floating gate layer disposed on the dielectric layer and extending at least partially into each of the plurality of trenches.Type: ApplicationFiled: April 4, 2018Publication date: October 10, 2019Inventors: Xiang-Zheng BO, John H. MACPEAK, Douglas T. GRIDER
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Publication number: 20190207025Abstract: In some examples, a transistor includes a first well doped with a first-type dopant having a first concentration. The transistor also includes a gate oxide layer on a portion of the first well and a gate layer on the gate oxide layer. The transistor further includes a first segment of a second well doped with the first-type dopant having a second concentration, the first segment underlapping a first portion of the gate layer. The transistor also includes a source region doped with a second-type dopant having a third concentration, the source region in the first segment. The transistor further includes a drain region doped with the second-type dopant having a concentration that is substantially the same as the third concentration.Type: ApplicationFiled: January 15, 2018Publication date: July 4, 2019Inventors: Xiang-Zheng BO, Michelle N. NGUYEN, Douglas T. GRIDER
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Patent number: 9881795Abstract: A method of manufacturing a semiconductor includes applying a planarization material to a substrate and forming an opening in the planarization material. The opening is filled with polysilicon. A plurality of etching modulation sequences are applied to the substrate, each of the etching modulation sequences including: applying a first etching process to the substrate, wherein the first etching process is more selective to polysilicon than the planarization material; and applying a second etching process to the substrate, wherein the second etching process is more selective to the planarization material than the polysilicon.Type: GrantFiled: October 7, 2016Date of Patent: January 30, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: David Gerald Farber, Ping Jiang, Brian K. Kirkpatrick, Douglas T. Grider, III
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Publication number: 20170148634Abstract: A method of manufacturing a semiconductor includes applying a planarization material to a substrate and forming an opening in the planarization material. The opening is filled with polysilicon. A plurality of etching modulation sequences are applied to the substrate, each of the etching modulation sequences including: applying a first etching process to the substrate, wherein the first etching process is more selective to polysilicon than the planarization material; and applying a second etching process to the substrate, wherein the second etching process is more selective to the planarization material than the polysilicon.Type: ApplicationFiled: October 7, 2016Publication date: May 25, 2017Inventors: David Gerald Farber, Ping Jiang, Brian K. Kirkpatrick, Douglas T. Grider, III
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Patent number: 9490143Abstract: A method of manufacturing a semiconductor includes applying a planarization material to a substrate and forming an opening in the planarization material. The opening is filled with polysilicon. A plurality of etching modulation sequences are applied to the substrate, each of the etching modulation sequences including: applying a first etching process to the substrate, wherein the first etching process is more selective to polysilicon than the planarization material; and applying a second etching process to the substrate, wherein the second etching process is more selective to the planarization material than the polysilicon.Type: GrantFiled: November 25, 2015Date of Patent: November 8, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: David Gerald Farber, Ping Jiang, Brian K. Kirkpatrick, Douglas T. Grider, III
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Patent number: 9431248Abstract: An integrated circuit containing an analog MOS transistor may be formed by implanting drain extensions with exactly four sub-implants wherein at least one sub-implant implants dopants in a substrate of the integrated circuit at a source/drain gate edge of the analog MOS transistor at a twist angle having a magnitude of 5 degrees to 40 degrees with respect to the source/drain gate edge of the analog MOS transistor, for each source/drain gate edge of the analog MOS transistor, wherein a zero twist angle sub-implant is perpendicular to the source/drain gate edge. No more than two sub-implants put the dopants in the substrate at any source/drain gate edge of the analog MOS transistor. All four sub-implants are performed at a same tilt angle. No halo implants are performed on the analog MOS transistor.Type: GrantFiled: October 2, 2015Date of Patent: August 30, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Xiang-Zheng Bo, Alwin Tsao, Douglas T. Grider
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Patent number: 9318337Abstract: An integrated circuit capacitor. The capacitor includes a substrate, a first conductor, and a first insulating region between the first conductor and the substrate. The capacitor also includes a second conductor, a second insulating region between the first conductor and the second conductor, a third conductor, and a third insulating region between the first conductor and the third conductor. The capacitor also includes a fourth conductor and a fourth insulating region between the first conductor and the fourth conductor.Type: GrantFiled: September 17, 2014Date of Patent: April 19, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Xiangzheng Bo, Douglas T. Grider
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Publication number: 20160027647Abstract: An integrated circuit containing an analog MOS transistor may be formed by implanting drain extensions with exactly four sub-implants wherein at least one sub-implant implants dopants in a substrate of the integrated circuit at a source/drain gate edge of the analog MOS transistor at a twist angle having a magnitude of 5 degrees to 40 degrees with respect to the source/drain gate edge of the analog MOS transistor, for each source/drain gate edge of the analog MOS transistor, wherein a zero twist angle sub-implant is perpendicular to the source/drain gate edge. No more than two sub-implants put the dopants in the substrate at any source/drain gate edge of the analog MOS transistor. All four sub-implants are performed at a same tilt angle. No halo implants are performed on the analog MOS transistor.Type: ApplicationFiled: October 2, 2015Publication date: January 28, 2016Inventors: Xiang-Zheng Bo, Alwin Tsao, Douglas T. Grider
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Patent number: 9177802Abstract: An integrated circuit containing an analog MOS transistor may be formed by implanting drain extensions with exactly four sub-implants wherein at least one sub-implant implants dopants in a substrate of the integrated circuit at a source/drain gate edge of the analog MOS transistor at a twist angle having a magnitude of 5 degrees to 40 degrees with respect to the source/drain gate edge of the analog MOS transistor, for each source/drain gate edge of the analog MOS transistor, wherein a zero twist angle sub-implant is perpendicular to the source/drain gate edge. No more than two sub-implants put the dopants in the substrate at any source/drain gate edge of the analog MOS transistor. All four sub-implants are performed at a same tilt angle. No halo implants are performed on the analog MOS transistor.Type: GrantFiled: December 27, 2013Date of Patent: November 3, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Xiang-Zheng Bo, Alwin Tsao, Douglas T. Grider
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Publication number: 20150076577Abstract: An integrated circuit capacitor. The capacitor includes a substrate, a first conductor, and a first insulating region between the first conductor and the substrate. The capacitor also includes a second conductor, a second insulating region between the first conductor and the second conductor, a third conductor, and a third insulating region between the first conductor and the third conductor. The capacitor also includes a fourth conductor and a fourth insulating region between the first conductor and the fourth conductor.Type: ApplicationFiled: September 17, 2014Publication date: March 19, 2015Inventors: Xiangzheng Bo, Douglas T. Grider