Patents by Inventor Douglas Ticknor Grider

Douglas Ticknor Grider has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11239346
    Abstract: A method of forming an integrated circuit relative to a wafer comprising a semiconductor substrate. The method first forms a first dielectric layer having a first thickness and along the substrate, the first forming step comprising plasma etching the wafer in a first substrate area and a second substrate area and thereafter growing the first dielectric layer in the first substrate area and the second substrate area. After the first step, the method second forms a second dielectric layer having a second thickness and along the substrate in the second substrate area, the second thickness less than the first thickness, the second forming step comprising removal of the first dielectric layer in the second substrate area without plasma and until a surface of the substrate is exposed and growing the second dielectric layer in at least a portion of the surface.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: February 1, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: John Howard MacPeak, Douglas Ticknor Grider, Brian K. Kirkpatrick
  • Patent number: 11205575
    Abstract: A method of forming an integrated circuit includes forming a first layer having a first material type over a first side of a semiconductor wafer. A second layer having a second different material type is removed from a second opposing side of the semiconductor wafer using a first process that removes the second material type at a greater rate than the first material type. Subsequent to removing the second layer, the first layer is removed using a second different process.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: December 21, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Byron Joseph Palla, Stephen Alan Keller, Brian Edward Hornung, Brian K. Kirkpatrick, Douglas Ticknor Grider
  • Publication number: 20200381541
    Abstract: A method of forming an integrated circuit relative to a wafer comprising a semiconductor substrate. The method first forms a first dielectric layer having a first thickness and along the substrate, the first forming step comprising plasma etching the wafer in a first substrate area and a second substrate area and thereafter growing the first dielectric layer in the first substrate area and the second substrate area. After the first step, the method second forms a second dielectric layer having a second thickness and along the substrate in the second substrate area, the second thickness less than the first thickness, the second forming step comprising removal of the first dielectric layer in the second substrate area without plasma and until a surface of the substrate is exposed and growing the second dielectric layer in at least a portion of the surface.
    Type: Application
    Filed: May 30, 2019
    Publication date: December 3, 2020
    Inventors: John Howard MacPeak, Douglas Ticknor Grider, Brian K. Kirkpatrick
  • Publication number: 20200343099
    Abstract: A method of forming an integrated circuit includes forming a first layer having a first material type over a first side of a semiconductor wafer. A second layer having a second different material type is removed from a second opposing side of the semiconductor wafer using a first process that removes the second material type at a greater rate than the first material type. Subsequent to removing the second layer, the first layer is removed using a second different process.
    Type: Application
    Filed: August 27, 2019
    Publication date: October 29, 2020
    Inventors: Byron Joseph Palla, Stephen Alan Keller, Brian Edward Hornung, Brian K. Kirpatrick, Douglas Ticknor Grider
  • Patent number: 5969397
    Abstract: A composite dielectric layer (102). A first layer (112) of the composite dielectric layer (102) has a small to no nitrogen concentration. A second layer (114) of the composite dielectric layer (102) has a larger nitrogen concentration (e.g., 5-15%). The composite dielectric layer (102) may be used as a thin gate dielectric wherein the second layer (114) is located adjacent a doped gate electrode (110) and has sufficient nitrogen concentration to stop penetration of dopant from the gate electrode (110) to the channel region (108). The first layer (112) is located between the second layer (114) and the channel region (108). The low nitrogen concentration of the first layer (112) is limited so as to not interfere with carrier mobility in the channel region (108).
    Type: Grant
    Filed: November 19, 1997
    Date of Patent: October 19, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Douglas Ticknor Grider, III, Paul Edward Nicollian, Steve Hsia