Abstract: A method is provided for forming a near infrared (NIR) active pixel sensor array on a silicon-on-insulator (SOI) substrate. The method forms a first wafer comprising a high resistance first Si substrate and a moderately doped first Si layer, and forms a second wafer comprising a first silicon oxide layer and a second Si layer. The method bonds the first wafer to the second wafer, forming a SOI substrate. Then, a diode is formed with a p-n junction space charge region extending into the first Si substrate. A thin-film transistor (TFT) is formed in the second Si layer, and interconnects are formed between the TFT and the diode. For example, first Si substrate may have a resistivity of greater than 100 ohm-cm, and the first Si layer may have a dopant concentration in the range of about 1×1016 to about 5×1018 cm?3.

Abstract: A device and associated method are provided for fabricating a liquid phase epitaxial (LPE) Germanium-on-Insulator (GOI) photodiode with buried high resistivity Germanium (Ge) layer. The method provides a silicon (Si) substrate, and forms a bottom insulator overlying the Si substrate with a Si seed access area. Then, a Ge P-I-N diode is formed with an n +-doped (n+) mesa, a p+-doped (p+) Ge bottom insulator interface and mesa lateral interface, and a high resistivity Ge layer interposed between the p+ Ge and n+ Ge. A metal electrode is formed overlying a region of the p+ Ge lateral interface, and a transparent electrode is formed overlying the n+ Ge mesa. In one aspect, the method deposits a silicon nitride layer temporary cap overlying the high resistivity Ge layer, and an annealing is performed to epitaxially crystallize the Ge bottom interface and high resistivity Ge layer.

Abstract: A method of fabricating a low, dark-current germanium-on-silicon PIN photo detector includes preparing a P-type silicon wafer; implanting the P-type silicon wafer with boron ions; activating the boron ions to form a P+ region on the silicon wafer; forming a boron-doped germanium layer on the P+ silicon surface; depositing an intrinsic germanium layer on the born-doped germanium layer; cyclic annealing, including a relatively high temperature first anneal step and a relatively low temperature second anneal step; repeating the first and second anneal steps for about twenty cycles, thereby forcing crystal defects to the P+ germanium layer; implanting ions in the surface of germanium layer to form an N+ germanium surface layer and a PIN diode; activating the N+ germanium surface layer by thermal anneal; and completing device according to known techniques to form a low dark-current germanium-on-silicon PIN photodetector.

Abstract: A method of fabricating a germanium photo detector includes preparing a silicon substrate wafer and depositing and planarizing a silicon oxide layer on the silicon substrate. Contact holes are formed in the silicon oxide layer. An N+ epitaxial germanium layer is grown on the silicon oxide layer and in the contact holes. An N+ germanium layer is formed by ELO. The structure is smoothed and thinned. An intrinsic germanium layer is grown on the N+ epitaxial germanium layer. A P+ germanium layer is formed on the intrinsic germanium layer and a silicon oxide overcoat is deposited. A window is opened through the silicon oxide overcoat to the P+ germanium layer. A layer of conductive material is deposited on the silicon oxide overcoat and in the windows therein. The conductive material is etched to form individual sensing elements.

Abstract: A method of fabricating a germanium photo detector includes preparing a silicon substrate; depositing and planarizing a silicon oxide layer; forming contact holes in the silicon oxide layer which communicate with the underlying silicon substrate; growing an epitaxial germanium layer of a first type on the silicon oxide layer and in the contact holes; growing an intrinsic germanium layer on the epitaxial germanium layer and any exposed silicon oxide layer; growing a germanium layer of a second type on the intrinsic germanium layer and any exposed silicon oxide layer; depositing a layer of covering material take from the group of materials consisting of polysilicon, polysilicon-germanium and In2O3—SnO2; and etching the covering material to form individual sensing elements.

Abstract: A SiGe surface-normal optical path photodetector structure and a method for forming the SiGe optical path normal structure are provided. The method comprises: forming a Si substrate with a surface; forming a Si feature, normal with respect to the Si substrate surface, such as a via, trench, or pillar; depositing SiGe overlying the Si normal feature to a thickness in the range of 5 to 1000 nanometers (nm); and, forming a SiGe optical path normal structure having an optical path length in the range of 0.1 to 10 microns. Typically, the SiGe has a Ge concentration in the range from 5 to 100%. The Ge concentration may be graded to increase with respect to the deposition thickness. For example, the SiGe may have a 20% concentration of Ge at the Si substrate interface, a 30% concentration of Ge at a SiGe film top surface, and a thickness of 400 nm.

Abstract: A floating body germanium (Ge) phototransistor with a photo absorption threshold bias region, and an associated fabrication process are presented. The method includes: providing a p-doped Silicon (Si) substrate; selectively forming an insulator layer overlying a first surface of the Si substrate; forming an epitaxial Ge layer overlying the insulator layer; forming a channel region in the Ge layer; forming a gate dielectric, gate electrode, and gate spacers; forming source/drain (S/D) regions in the Ge layer; and, forming a photo absorption threshold bias region in the Ge layer, adjacent the channel region. In one aspect, the second S/D region has a length, longer than the first S/D length. The photo absorption threshold bias region underlies the second S/D region. Alternately, the second S/D region is separated from the channel by an offset, and the photo absorption threshold bias region is the offset in the Ge layer, after a light p-doping.

Abstract: A method of controlling strain in a single-crystal, epitaxial oxide film, includes preparing a silicon substrate; forming a silicon alloy layer taken from the group of silicon alloy layer consisting of Si1-xGex and Si1-yCy on the silicon substrate; adjusting the lattice constant of the silicon alloy layer by selecting the alloy material content to adjust and to select a type of strain for the silicon alloy layer; depositing a single-crystal, epitaxial oxide film, by atomic layer deposition, taken from the group of oxide films consisting of perovskite manganite materials, single crystal rare-earth oxides and perovskite oxides, not containing manganese; and rare earth binary and ternary oxides, on the silicon alloy layer; and completing a desired device.

Abstract: A floating body germanium (Ge) phototransistor and associated fabrication process are presented. The method includes: providing a silicon (Si) substrate; selectively forming an insulator layer overlying the Si substrate; forming an epitaxial Ge layer overlying the insulator layer using a liquid phase epitaxy (LPE) process; forming a channel region in the Ge layer; forming a gate dielectric, gate electrode, and gate spacers overlying the channel region; and, forming source/drain regions in the Ge layer. The LPE process involves encapsulating the Ge with materials having a melting temperature greater than a first temperature, and melting the Ge using a temperature lower than the first temperature. The LPE process includes: forming a dielectric layer overlying deposited Ge; melting the Ge; and, in response to cooling the Ge, laterally propagating an epitaxial growth front into the Ge from an underlying Si substrate surface.

Abstract: A method of fabricating a silicon-germanium CMOS includes preparing a silicon substrate wafer; depositing an insulating layer on the silicon substrate wafer; patterning and etching the insulating layer; depositing a layer of polycrystalline germanium on the insulating layer and on at least a portion of the silicon substrate wafer; patterning and etching the polycrystalline germanium; encapsulating the polycrystalline germanium with an insulating material; rapidly thermally annealing the wafer at a temperature sufficient to melt the polycrystalline germanium; cooling the wafer to promote liquid phase epitaxy of the polycrystalline germanium, thereby forming a single crystal germanium layer; and completing the CMOS device.

Abstract: A method of fabricating resistor memory array includes preparing a silicon substrate; depositing a bottom electrode, a sacrificial layer, and a hard mask layer on a substrate P+ layer; masking, patterning and etching to remove, in a first direction, a portion of the hard mask, the sacrificial material, the bottom electrode; depositing a layer of silicon oxide; masking, patterning and etching to remove, in a second direction perpendicular to the first direction, a portion of the hard mask, the sacrificial material, the bottom electrode;, and over etching to an N+ layer and at least 100 nm of the silicon substrate; depositing of a layer of silicon oxide; etching to remove any remaining hard mask and any remaining sacrificial material; depositing a layer of CMR material; depositing a top electrode; applying photoresist, patterning the photoresist and etching the top electrode; and incorporating the memory array into an integrated circuit.

Abstract: A high-density Germanium (Ge)-on-Insulator (GOI) photodiode array and corresponding fabrication method are provided. The method includes: forming an array of pixel driver nMOST devices, each device having a gate connected to a row line in a first orientation, a first source/drain (S/D) region, and a second S/D region connected to Vdd; forming a P-I-N Ge diode for each pixel as follows: forming a n+ region; forming an intrinsic Ge region overlying the n+ region; forming a p+ junction in the intrinsic Ge; and, isolating the P-I-N Ge diodes; and, forming an Indium Tin oxide (ITO) column in a second orientation, about orthogonal to the first orientation, overlying the P-I-N Ge diodes.

Abstract: A method of fabricating a germanium infrared sensor for a CMOS imager includes preparation a donor wafer, including: ion implantation into a silicon wafer to form a P+ silicon layer; growing an epitaxial germanium layer on the P+ silicon layer, forming a silicon-germanium interface; cyclic annealing; and implanting hydrogen ions to a depth at least as deep as the P+ silicon layer to form a defect layer; preparing a handling wafer, including: fabricating a CMOS integrated circuit on a silicon substrate; depositing a layer of refractory metal; treating the surfaces of the donor wafer and the handling wafer for bonding; bonding the handling wafer and the donor wafer to form a bonded structure; splitting the bonded structure along the defect layer; depositing a layer of indium tin oxide on the germanium layer; completing the IR sensor.

Abstract: A method is provided for forming a liquid phase epitaxial (LPE) germanium (Ge)-on-insulator (GOI) thin-film with a smooth surface. The method provides a silicon (Si) wafer, forms a silicon nitride insulator layer overlying the Si wafer, and selectively etches the silicon nitride insulator layer, forming a Si seed access region. Then, the method conformally deposits Ge overlying the silicon nitride insulator layer and Si seed access region, forming a Ge layer with a first surface roughness, and smoothes the Ge layer using a chemical-mechanical polish (CMP) process. Typically, the method encapsulates the Ge layer and anneals the Ge layer to form a LPE Ge layer. A Ge layer is formed with a second surface roughness, less than the first surface roughness. In some aspects, the method forms an active device in the LPE Ge layer.

Abstract: A method of making CMOS devices on strained silicon on glass includes preparing a glass substrate, including forming a strained silicon layer on the glass substrate; forming a silicon oxide layer by plasma oxidation of the strained silicon layer; depositing a layer of doped polysilicon on the silicon oxide layer; forming a polysilicon gate; implanting ions to form a LDD structure; depositing and forming a spacer dielectric on the gate structure; implanting and activation ions to form source and drain structures; depositing a layer of metal film; annealing the layer of metal film to form salicide on the source, drain and gate structures; removing any unreacted metal film; depositing a layer of interlayer dielectric; and forming contact holes and metallizing.

Abstract: Provided are a SiGe vertical optical path and a method for selectively forming a SiGe optical path normal structure for IR photodetection. The method comprises: forming a Si substrate surface; forming a Si feature, normal with respect to the Si substrate surface, such as a trench, via, or pillar; and, selectively forming a SiGe optical path overlying the Si normal feature. In some aspects, the Si substrate surface is formed a first plane and the Si normal feature has walls (sidewalls), normal with respect to the Si substrate surface, and a surface in a second plane, parallel to the first plane. Then, selectively forming a SiGe optical path overlying the Si normal feature includes forming a SiGe vertical optical path overlying the normal feature walls.

Abstract: A method of fabricating a biaxial tensile strained layer for NMOS fabrication and a uniaxial compressive strained layer for PMOS fabrication on a single wafer for use in CMOS ICs, includes preparing a silicon substrate for CMOS fabrication; depositing, patterning and etching a first and second insulating layers; removing a portion of the second insulating layer from a PMOS active area; depositing a layer of epitaxial silicon on the PMOS active area; removing a portion of the second insulating layer from an NMOS active area; growing an epitaxial silicon layer and growing an epitaxial SiGe layer on the NMOS active area; implanting H2+ ions; annealing the wafer to relax the SiGe layer; removing the remaining second insulating layer from the wafer; growing a layer of silicon; finishing a gate module; depositing a layer of SiO2 to cover the NMOS wafer; etching silicon in the PMOS active area; selectively growing a SiGe layer on the PMOS active area; wherein the silicon layer in the NMOS active area is under biaxia

Abstract: Disclosing is a strained silicon finFET device having a strained silicon fin channel in a double gate finFET structure. The disclosed finFET device is a double gate MOSFET consisting of a silicon fin channel controlled by a self-aligned double gate for suppressing short channel effect and enhancing drive current. The silicon fin channel of the disclosed finFET device is a strained silicon fin channel, comprising a strained silicon layer deposited on a seed fin having different lattice constant, for example, a silicon layer deposited on a silicon germanium seed fin, or a carbon doped silicon layer deposited on a silicon seed fin. The lattice mismatch between the silicon layer and the seed fin generates the strained silicon fin channel in the disclosed finFET device to improve hole and electron mobility enhancement, in addition to short channel effect reduction characteristic inherently in a finFET device.

Abstract: A method of fabricating a thin film germanium photodetector includes preparing a silicon substrate; fabricating a CMOS device on the silicon substrate; preparing a germanium substrate; preparing surfaces of each substrate for bonding; bonding the germanium substrate to the CMOS-bearing silicon substrate to form a bonded structure; removing a portion of the germanium substrate from the bonded structure; forming a PIN diode in the germanium substrate; removing a portion of the germanium layer by etching; and completing the germanium photo detector.

Abstract: A method of fabricating a low defect germanium thin film includes preparing a silicon wafer for germanium deposition; forming a germanium film using a two-step CVD process, annealing the germanium thin film using a multiple cycle process; implanting hydrogen ions; depositing and smoothing a layer of tetraethylorthosilicate oxide (TEOS); preparing a counter wafer; bonding the germanium thin film to a counter wafer to form a bonded structure; annealing the bonded structure at a temperature of at least 375° C. to facilitate splitting of the bonded wafer; splitting the bonded structure to expose the germanium thin film; removing any remaining silicon from the germanium thin film surface along with a portion of the germanium thin film defect zone; and incorporating the low-defect germanium thin film into the desired end-product device.