Abstract: A passive matching network is connected to an input/output line for an automatic test equipment drive channel to compensate for capacitances associated with a receiver circuit connected to the line, and also an optional current-mode driver circuit. The matching circuit preferably comprises a T-coil circuit that can include a bridging capacitor; separate T-coil circuits can be provided to separately compensate for receiver circuit and current-mode driver circuit capacitances. The driver and receiver circuits can be implemented on a common layer of an integrated circuit, with the T-coil windings implemented in a separate layer of the same integrated circuit that is spaced from the common layer by at least one dielectric layer.

Abstract: A passive matching network is connected to an input/output line for an automatic test equipment drive channel to compensate for capacitances associated with a receiver circuit connected to the line, and also an optional current-mode driver circuit. The matching circuit preferably comprises a T-coil circuit that can include a bridging capacitor; separate T-coil circuits can be provided to separately compensate for receiver circuit and current-mode driver circuit capacitances. The driver and receiver circuits can be implemented on a common layer of an integrated circuit, with the T-coil windings implemented in a separate layer of the same integrated circuit that is spaced from the common layer by at least one dielectric layer.

Abstract: A passive matching network is connected to an input/output line for an automatic test equipment drive channel to compensate for capacitances associated with a receiver circuit connected to the line, and also an optional current-mode driver circuit. The matching circuit preferably comprises a T-coil circuit that can include a bridging capacitor; separate T-coil circuits can be provided to separately compensate for receiver circuit and current-mode driver circuit capacitances. The driver and receiver circuits can be implemented on a common layer of an integrated circuit, with the T-coil windings implemented in a separate layer of the same integrated circuit that is spaced from the common layer by at least one dielectric layer.

Abstract: A circuit testing apparatus for testing a circuit under test. The circuit testing apparatus includes a controller for controlling signals being transferred between a circuit under test and the circuit testing apparatus. The circuit testing apparatus further includes a driver circuit for generating signals to be applied to the circuit under test. The driver includes a high speed slave chain and DC control loop chain coupled to the circuit under test. The high speed slave chain receives a differential voltage logic pulse train and converts the logic pulse train into a high speed current steering for producing the drive signal to be applied to the circuit under test. The DC control loop chain provides feedback paths for DC regulation of inputs of the high speed slave chain.

Abstract: A circuit testing apparatus includes a controlling processor for controlling stimulus signals to be applied to a circuit under test and for processing and storing response signals generated by the circuit under test in response to the stimulus signals. The stimulus signals are generated by a driver portion of a receiver/driver circuit coupled to a pin on the circuit under test. The driver includes an output stage circuit coupled to the pin on the circuit under test. The output stage circuit includes a linear amplifier circuit which receives a control signal via the controlling processor and generates from the control signal a drive signal to be applied to the circuit under test. The linear amplifier allows the driver to produce a drive signal with a high level of voltage and timing accuracy and, in the case of digital square pulse signals, a high level of pulse symmetry.

Abstract: A circuit testing apparatus includes a controlling processor for controlling stimulus signals to be applied to a circuit under test and for processing and storing response signals generated by the circuit under test in response to the stimulus signals. The stimulus signals are generated by a driver portion of a receiver/driver circuit coupled to a pin on the circuit under test. The driver includes an output stage circuit coupled to the pin on the circuit under test. The output stage circuit includes a linear amplifier circuit which receives a control signal via the controlling processor and generates from the control signal a drive signal to be applied to the circuit under test. The linear amplifier allows the driver to produce a drive signal with a high level of voltage and timing accuracy and, in the case of digital square pulse signals, a high level of pulse symmetry.

Abstract: A circuit testing apparatus for testing a circuit under test. The circuit testing apparatus includes a controller for controlling signals being transferred between a circuit under test and the circuit testing apparatus. The circuit testing apparatus further includes a driver circuit for generating signals to be applied to the circuit under test. The driver includes a high speed slave chain and DC control loop chain coupled to the circuit under test. The high speed slave chain receives a differential voltage logic pulse train and converts the logic pulse train into a high speed current steering for producing the drive signal to be applied to the circuit under test. The DC control loop chain provides feedback paths for DC regulation of inputs of the high speed slave chain.

Abstract: A parasitic capacitance cancellation circuit for a direct bonded silicon-on-insulator integrated circuit includes one or more transistors fabricated silicon-on-insulator; a silicon substrate region outside the transistor(s) having a parasitic capacitance to be cancelled; a bootstrap terminal connected to the region outside the transistor(s); and a unity gain buffer responsive to the output of the transistor(s) and having its output connected to the bootstrap terminals for providing a voltage to the region outside the transistor(s) which follows the voltage developed on the parasitic capacitance and nullifies the parasitic capacitance.

Abstract: A circuit for varying the temperature of a first bipolar transistor in order to thermally compensate for self-heating effects of an associated device in a common signal path with the first transistor, the first transistor being configured within an isolated collector region. The circuit includes a second bipolar transistor provided within the isolated collector region and thermally coupled to the first transistor, the second transistor operable for providing heat to the first transistor to alter the temperature to a predetermined level, thus changing the operational voltage characteristics of the first transistor so as to minimize shifts in offset voltage.

Abstract: Automatic test equipment (ATE) for post-production testing of multi-pin integrated circuits (ICs). Each pin is assigned to a pin card having a pin driver and an active load with the latter including both a current source and a current sink. The pin driver and active load are connectable alternatively to the IC pin in response to complementary inhibit signals. Within the active load, the source and sink and connected/disconnected by respective pairs of matched transistor switch circuits the individual switches of which are alternatively activatable by differential control means. Both switch circuits of each pair are supplied from a single current source. One switch circuit of each pair, when activated, directs the current from the single current source to (from) the IC pin, while the other switch circuit, when activated, directs the current to (from) a return line.