Abstract: A waveguide assembly integrated with a semiconductor wafer is provided. The waveguide assembly includes a waveguide channel defined by internal walls of the wafer lined with a metallic layer, and having at least one port for transmission of the RF signal into or out of the waveguide channel. The waveguide assembly also includes a semiconductor obstacle member disposed in the waveguide channel. The waveguide assembly may be fabricated using etching and deposition processes for semiconductor devices. In use, selectively varying either one or both of frequency or power level of electromagnetic radiation applied to the obstacle member varies electrical conductance of the obstacle member, and thereby varies the electrical impedance of the obstacle member to transmission of the RF signal through the waveguide channel. The waveguide assembly may be used for switching, attenuating, routing, filtering, and transforming the RF signal.

Abstract: An active via is taught which comprises at least one via and at least one transistor which acts as a switch element. The resulting active via can be used with 1D, 2.5D or 3D chips to: control circuit elements; reduce EMI between vias; increase the density of vias; improve power and thermal efficiencies of chips; simplify power, data and other routing networks on chips; enable a higher level stacking of dies or layers in a chip while maintaining modularity; etc. A control strategy system can be provided to remove the supply of power to one or more regions of the chip when the regions are not in use and to supply power to those regions when the regions are in use, or to control input and output to regions of the chip. The active vias can be fabricated with Back or Front End Of Line processes.

Abstract: Novel semiconductor devices are taught. The novel devices include a thin film transistor (TFT) with an n-type semiconductor layer to form a channel between a source and a drain. The TFT further includes a source-channel interfacial member adjacent to at least the source contact of the device to provide depletion layer control of the operation of the TFT.

Abstract: Novel semiconductor devices are taught. The novel devices include a thin film transistor (TFT) with an n-type semiconductor layer to form a channel between a source and a drain. The TFT further includes a source-channel interfacial member adjacent to at least the source contact of the device to provide depletion layer control of the operation of the TFT.

Abstract: A first of its kind polycrystalline or amorphous-based tunneling thin-film junction transistor (TJT) utilizing bipolar charge transport with a very high current density is introduced. Using the TJT architecture, this thin-film transistor (TFT) performs robustly at collector voltages at fields greater than 0.5 MV/cm with the current density output greater than 1 mA/mm without any observed electrical breakdown. Combining the principles of the tunneling emitter and the base inversion channel, the high-k dielectric/wideband gap amourphous or polycrystalline substrate/with p-type semiconductor substrate behaved most analogously to a bipolar transistor.

Abstract: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate. After forming a silicon nitride layer on the high-k gate dielectric layer, a gate electrode is formed on the silicon nitride layer.

Abstract: A method of forming a dielectric layer suitable for use as the gate dielectric layer in a MOSFET includes passivating the surface of a semiconductor substrate at a temperature less than approximately 80° C. and nitridizing the passivation layer. In particular embodiments, passivating a silicon wafer includes forming a hydroxy-silicate layer at approximately 24° C. In a further aspect of the present invention, an integrated circuit includes a plurality of insulated gate field effect transistors, wherein various ones of the plurality of transistors have gate dielectric layers of the nitridized passivation layer.

Abstract: A method of forming a dielectric layer suitable for use as the gate dielectric layer in a MOSFET includes passivating the surface of a semiconductor substrate at a temperature less than approximately 80° C. and nitridizing the passivation layer. In particular embodiments, passivating a silicon wafer includes forming a hydroxy-silicate layer at approximately 24° C. In a further aspect of the present invention, an integrated circuit includes a plurality of insulated gate field effect transistors, wherein various ones of the plurality of transistors have gate dielectric layers of the nitridized passivation layer.

Abstract: A method of forming a dielectric layer suitable for use as the gate dielectric layer in a MOSFET includes passivating the surface of a semiconductor substrate at a temperature less than approximately 80° C. and nitridizing the passivation layer. In particular embodiments, passivating a silicon wafer includes forming a hydroxy-silicate layer at approximately 24° C. In a further aspect of the present invention, an integrated circuit includes a plurality of insulated gate field effect transistors, wherein various ones of the plurality of transistors have gate dielectric layers of the nitridized passivation layer.