Abstract: A technique for developing an inspection program for a circuit board to be run on an AOI system includes determining a characteristic, such as average gray level, of each window of the circuit board. The positions of the windows are varied slightly to simulate expected errors in the placement of the windows relative to the circuit board. After varying the positions of the windows, the characteristic of each window is determined again. Different values of the characteristic corresponding to slightly different positions are compared for each window. Values that substantially change for a window indicate a strong sensitivity to position. These windows may be reported to a programmer for corrective action.

Abstract: An automated optical inspection system includes a plurality of asynchronously triggerable cameras for providing image data of an object, such as a printed circuit board. The circuit board is divided into fields of view that are to be imaged in one or more cameras in one or more lighting modes. Each location on the board can be imaged by each camera in a plurality of lighting modes in a single pass across the board. The image data for each of the cameras can be concurrently transferred directly to main memory for opportunistic analysis by the main computer. The system allows the full bandwidth of the cameras to be utilized for reducing the inspection time of the board.

Abstract: A technique for developing an inspection program for a circuit board to be run on an AOI system includes determining a characteristic, such as average gray level, of each window of the circuit board. The positions of the windows are varied slightly to simulate expected errors in the placement of the windows relative to the circuit board. After varying the positions of the windows, the characteristic of each window is determined again. Different values of the characteristic corresponding to slightly different positions are compared for each window. Values that substantially change for a window indicate a strong sensitivity to position. These windows may be reported to a programmer for corrective action.

Abstract: A system and method for compensating pixel values in an inspection machine for inspecting printed circuit boards includes an image acquisition system for providing pixel values from a digitized image to a compensation circuit. The compensation circuit applies one or more compensation values to the digitized pixel values to provide compensated digitized pixel values for storage in a memory. The compensated digitized pixel values are then available for use by an image processor which implements inspection techniques during a printed circuit board manufacturing process. With this technique, the system corrects the errors on a pixel by pixel basis as the pixel values representing an image of a printed circuit board are transferred from the image acquisition system to the memory.

Abstract: Method and apparatus for providing dynamic testing of electronic assemblies during their manufacture. A production line includes a communication network to interconnect assembly and inspection equipment. Events impacting the manufacture of the assemblies are communicated among the equipment, allowing the testing to be dynamically adjusted in response to events. Dynamic adjustment allows the process to quickly detect defects introduced by events. The concept is illustrated with a production line that has a pick and place machine and an inspection station. When an operator changes a reel of components at the pick and place machine, the inspection station will switch test programs to quickly verify that the correct reel has been loaded.

Abstract: An automated optical inspection (AOI) system includes component learning integrated with the inspection of a circuit board. The AOI system includes a component learning area that can be viewed by an imaging system used to inspect the circuit board in an inspection area. The component learning area can correspond to a region proximate the inspection area. The automated optical inspection system receives board inspection and component learn requests and determines opportune times to learn new component characteristics during the board inspection process so as to minimize the impact of the learning process on the overall inspection efficiency.

Abstract: Method and apparatus for providing dynamic testing of electronic assemblies during their manufacture. A production line includes a communication network to interconnect assembly and inspection equipment. Events impacting the manufacture of the assemblies are communicated among the equipment, allowing the testing to be dynamically adjusted in response to events. Dynamic adjustment allows the process to quickly detect defects introduced by events. The concept is illustrated with a production line that has a pick and place machine and an inspection station. When an operator changes a reel of components at the pick and place machine, the inspection station will switch test programs to quickly verify that the correct reel has been loaded.

Abstract: A manufacturing defect analyzer, for inspecting assembled printed circuit boards, including a light source, an optical receiver, a computer controller, and a memory. A plurality of key-points are specified for each component mounted to a printed circuit board. A data record characterizing each key-point is then stored in memory. Next, the defect analyzer measures the height of selected key-points relative to reference key-points for each component. Finally, the measured heights are compared with limit values, thereby determining whether each component is defectively attached to the printed circuit board. The data records facilitate inspection of printed circuit boards having components that are available in different package types.

Abstract: A test system for multi-chip modules. Test points on the multi-chip modules are brought to the perimeter of the modules for easy access. The test points are grouped in arrays with an associated alignment post. The multi-chip module is probed with several independently positionable probes, each one of which can be independently aligned with one of the arrays of test points. Independent alignment of the test probes relaxes tolerances on the test points needed to ensure proper contact between the test pints and the probes. As a result, the test points can be made very small, thereby reducing the amount of the multi-chip module dedicated for testing. In the preferred embodiment, the probes are made using flex circuits.

Abstract: A manufacturing defect analyzer, for inspecting assembled printed circuit boards, including a light source, an optical receiver, a computer controller, and a memory. A plurality of key-points are specified for each component mounted to a printed circuit board. A data record characterizing each key-point is then stored in memory. Next, the defect analyzer measures the height of selected key-points relative to reference key-points for each component. Finally, the measured heights are compared with limit values, thereby determining whether each component is defectively attached to the printed circuit board. The data records facilitate inspection of printed circuit boards having components that are available in different package types.

Abstract: A method and apparatus is presented for the automatic generation of boundary scan description language files for integrated circuits incorporating boundary scan circuitry of indeterminate configuration. The user enters basic pin information for the integrated circuit under consideration, along with an identification of which pins are the boundary-scan TAP pins and which are the power and ground pins. The user connects the pins of a sample integrated circuit to the test channels of the apparatus of the invention.

Abstract: A minimal memory in-circuit digital tester with vector memory concentrated in a centralized vector processor circuit, eliminating the need for pin memory. The vector processor circuit memory is partitioned into two blocks, a pointer memory and a change list memory. Every vector clock cycle has one pointer memory entry. The pointer memory entry is an address for the change list memory. The change list memory contains lists of nodes used in the vector test sequence. Each change list entry contains a pin number and several control bits. The control bits define functions such as whether the pin will toggle its data or enable state, whether there are more pins in that particular change list, and whether the list or test has ended. When the end of each change list is reached, all pins that have been primed by that change list will be toggled. The next entry of the pointer memory is then selected which, in turn, selects another, or perhaps the same change list in the change list memory.

Abstract: A glove is equipped with a mouthpiece containing an air passage. The mouthpiece allows the wearer to puff air into the space between the glove and the skin of the hand. The puffed up glove is much easier to doff and don than a conventional glove. A puff-off wetsuit glove for use in underwater activities is described in detail.

Abstract: A method of detecting possibly electrically-open connections between circuit nodes and pins of components physically connected to the nodes. The pins include input pins and output pins, the input pins connected to corresponding input nodes and the output pins connected to corresponding output nodes. The method comprises the steps of determining if the connections between the input pins and the input nodes can be tested, and then testing for an electrically-open connection between each input pin and its corresponding input node. The two-step method of determining if the connections between the input pins and the input nodes can be tested includes a first step of determining if the output nodes exhibit activity in response to application of stimuli to the input nodes, and continuing testing if there is activity. The second step is determining if each output node exhibits a signature repeated identically in response to stimuli repeated identically at all the input nodes.

Abstract: An apparatus for the automatic, in-circuit testing of the electrical properties of complex digital integrated circuit assemblies is disclosed. A programmed processor is provided to control a set of selectable switches, which connect selected nodes of a circuit under test to certain ones of a plurality of signal lines. One of the signal lines supplies a selected digital test signal from a set of selectable test signals to the selected node. The set of test signals including a Gray code. Another of the signal lines provides a response line connecting a selected node to a functional tester that performs one of a selectable number of intermediate functional tests. One of the functional tests is a signature analysis of the digital response signal in accordance with a cyclic redundancy check (CRC) coding technique.

Abstract: A method and apparatus for the high-speed testing of capacitors. A computing amplifier is connected with the capacitor under test to form an integrator which integrates a known excitation signal. The integration is initiated with no charge stored by the capacitor and at a zero crossing of the excitation signal. The integration occurs over a period which produces the maximum voltage across the capacitor. A peak detector measures the maximum voltage across the capacitor to produce a peak detection voltage inversely proportional to the value of the capacitor and directly proportional to a predetermined nominal value of the capacitor. The reciprocal of the output from the peak detector is formed to provide a measurement directly proportional to the capacitor value and inversely proportional to the nominal value of the capacitor.

Abstract: A method and apparatus for automatic, programmed, in-circuit component testing and functional testing. A multi-mode measurement unit having an exciter circuit, computing circuit, and a converter circuit is provided for measuring electrical signals. The measurement unit is controlled by a program-commanded measurement unit controller. A plurality of device connection switches are provided for connecting, by a program-commanded switch controller, the computing circuit to selected nodes of a circuit under test. The switch controller and the measurement unit controller receive commands from a programmed processor which executes stored programs of instruction. The programs contain subroutines which correlate with commanded measurement parameters and sequences within the measurement unit.

Abstract: An apparatus for the automatic, in-circuit testing of the electrical properties of complex digital integrated circuit assemblies is disclosed. A programmed processor is provided to control a set of selectable switches, which connect selected nodes of a circuit under test to certain ones of a plurality of signal lines. One of the signal lines supplies a selected digital test signal from a set of selectable test signals to the selected node. The set of test signals including a Gray code. Another of the signal lines provides a response line connecting a selected node to a functional tester that performs one of a selectable number of intermediate functional tests. One of the functional tests is a signature analysis of the digital response signal in accordance with a cyclic redundancy check (CRC) coding technique.