Abstract: A circuit for generating a speed value corresponding to a rotational frequency of a rotating shaft. A digital tachometer circuit has a tachometer circuit and a copy/hold circuit. The tachometer circuit maintains an intermediate speed value which is incremented by a gain constant as the rotational frequency increases and is decremented as the rotational frequency decreases. The copy/hold circuit samples the intermediate speed value at selected intervals, thus generating the speed value. The speed value is displayed to a user and represents the vehicle's speed.

Abstract: A serial pulse frequency converter is disclosed of the type which counts high frequency clock pulses between input pulses, multiplies each successive count by first and second proportionally constants and downcounts the products by high frequency clock pulses to produce output pulses at a new, proportional frequency. A first serial register is used to both count the high frequency pulses between input pulses and hold the count during the multiplication process. It is loaded at the end of multiplication with the a number representing the "lost counts" as it is switched to its counting mode. A second serial register accumulates the sum of partial products of the count and the proportionality constants. The gain circuit serially provides a first proportionality constant and then a second, but may selectively substitute a binary number representing a constant unity for the second.

Abstract: A digital speed control system including a processor performing arithmetical and logic operations in response to command inputs from the operator to maintain the present vehicle speed, to accelerate at a substantially constant rate to a new cruising speed or to a previously established cruising speed is disclosed. Certain processor operations are phased to speed sensor pulses to permit rate of change of speed computations to be performed with minimum hardware.

Abstract: Circuitry for developing a binary number proportional to the frequency of an input signal includes a first and second shift register and an adder. Timing control circuitry establishes a 16 bit computation period and also develops a fixed binary number. Circuit means are provided for interconnecting the adder and the firsrt register for increasing the content of the register by the fixed binary number once each cycle of the input signal and for reducing the content of the register by a fixed proportion each of the computation periods occurring during each cycle of the input signal. The content of the first register is transferred to the second or buffer register each cycle of the input signal and display means are provided for displaying the input frequency of a function as the binary number contained in the second register.