Patents by Inventor Douglas Ward Thomas

Douglas Ward Thomas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220338355
    Abstract: The present invention relates to printed circuit boards (PCBs), and more particularly, to methods of forming high aspect ratio through holes and high precision stub removal in a printed circuit board (PCB). The high precision stub removal processes may be utilized in removing long stubs and short stubs. In the methods, multiple holes of varying diameter and depth are drilled from an upper and/or lower surface of the printed circuit board utilizing drills of different diameters.
    Type: Application
    Filed: June 24, 2022
    Publication date: October 20, 2022
    Inventors: Douglas Ward THOMAS, Shinichi IKETANI, Dale KERSTEN
  • Patent number: 11399439
    Abstract: The present invention relates to printed circuit boards (PCBs), and more particularly, to methods of forming high aspect ratio through holes and high precision stub removal in a printed circuit board (PCB). The high precision stub removal processes may be utilized in removing long stubs and short stubs. In the methods, multiple holes of varying diameter and depth are drilled from an upper and/or lower surface of the printed circuit board utilizing drills of different diameters.
    Type: Grant
    Filed: January 21, 2019
    Date of Patent: July 26, 2022
    Assignee: SANMINA CORPORATION
    Inventors: Douglas Ward Thomas, Shinichi Iketani, Dale Kersten
  • Patent number: 10811210
    Abstract: A method of making printed circuit board vias using a double drilling and plating method is disclosed. A first hole is drilled in a core, the first hole having a first diameter. The first hole is filled and/or plated with an electrically conductive material. A circuit pattern may be formed on one or two conductive layers of the core. A multilayer structure may then be formed including a plurality of cores that also include pre-drilled and plated via holes, wherein at least some of the pre-drilled and plated via holes are aligned with the first hole. A second hole is then drilled within the first hole and the aligned pre-drilled and plated holes, the second hole having a second diameter where the second diameter is smaller than the first diameter. A conductive material is then plated to an inner surface of the second hole.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: October 20, 2020
    Assignee: Sanmina Corporation
    Inventors: Shinichi Iketani, Douglas Ward Thomas
  • Publication number: 20200043690
    Abstract: A method of making printed circuit board vias using a double drilling and plating method is disclosed. A first hole is drilled in a core, the first hole having a first diameter. The first hole is filled and/or plated with an electrically conductive material. A circuit pattern may be formed on one or two conductive layers of the core. A multilayer structure may then be formed including a plurality of cores that also include pre-drilled and plated via holes, wherein at least some of the pre-drilled and plated via holes are aligned with the first hole. A second hole is then drilled within the first hole and the aligned pre-drilled and plated holes, the second hole having a second diameter where the second diameter is smaller than the first diameter. A conductive material is then plated to an inner surface of the second hole.
    Type: Application
    Filed: October 14, 2019
    Publication date: February 6, 2020
    Inventors: Shinichi Iketani, Douglas Ward Thomas
  • Patent number: 10446356
    Abstract: A method of making printed circuit board vias using a double drilling and plating method is disclosed. A first hole is drilled in a core, the first hole having a first diameter. The first hole is filled and/or plated with an electrically conductive material. A circuit pattern may be formed on one or two conductive layers of the core. A multilayer structure may then be formed including a plurality of cores that also include pre-drilled and plated via holes, wherein at least some of the pre-drilled and plated via holes are aligned with the first hole. A second hole is then drilled within the first hole and the aligned pre-drilled and plated holes, the second hole having a second diameter where the second diameter is smaller than the first diameter. A conductive material is then plated to an inner surface of the second hole.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: October 15, 2019
    Assignee: SANMINA CORPORATION
    Inventors: Shinichi Iketani, Douglas Ward Thomas
  • Publication number: 20190159346
    Abstract: The present invention relates to printed circuit boards (PCBs), and more particularly, to methods of forming high aspect ratio through holes and high precision stub removal in a printed circuit board (PCB). The high precision stub removal processes may be utilized in removing long stubs and short stubs. In the methods, multiple holes of varying diameter and depth are drilled from an upper and/or lower surface of the printed circuit board utilizing drills of different diameters.
    Type: Application
    Filed: January 21, 2019
    Publication date: May 23, 2019
    Inventors: Douglas Ward THOMAS, Shinichi IKETANI, Dale KERSTEN
  • Patent number: 10188001
    Abstract: The present invention relates to printed circuit boards (PCBs), and more particularly, to methods of forming high aspect ratio through holes and high precision stub removal in a printed circuit board (PCB). The high precision stub removal processes may be utilized in removing long stubs and short stubs. In the methods, multiple holes of varying diameter and depth are drilled from an upper and/or lower surface of the printed circuit board utilizing drills of different diameters.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: January 22, 2019
    Assignee: SANMINA CORPORATION
    Inventors: Douglas Ward Thomas, Shinichi Iketani, Dale Kersten
  • Publication number: 20180110133
    Abstract: A method of making printed circuit board vias using a double drilling and plating method is disclosed. A first hole is drilled in a core, the first hole having a first diameter. The first hole is filled and/or plated with an electrically conductive material. A circuit pattern may be formed on one or two conductive layers of the core. A multilayer structure may then be formed including a plurality of cores that also include pre-drilled and plated via holes, wherein at least some of the pre-drilled and plated via holes are aligned with the first hole. A second hole is then drilled within the first hole and the aligned pre-drilled and plated holes, the second hole having a second diameter where the second diameter is smaller than the first diameter. A conductive material is then plated to an inner surface of the second hole.
    Type: Application
    Filed: October 13, 2017
    Publication date: April 19, 2018
    Inventors: Shinichi Iketani, Douglas Ward Thomas
  • Patent number: 9661758
    Abstract: Cost effective and efficient methods to maximize printed circuit board (PCB) utilization with minimized signal degradation are provided. The methods include electrically isolating a segmented via structure by controlling the formation of a conductive material within a plated via structure by utilizing different diameter drills within a via structure for trimming the conductive material at the via shoulder (i.e., the rim of a drilled two diameter hole boundary). The trimmed portion may be voided in the via structure for allowing electrically isolated plated through-hole (PTH) segments. One or more areas of trimmed rims within the via structure are used to form multiple stair like diameter holes to create one or more voids in the via structure. As a result, the formation of conductive material within the via structure may be limited to those areas necessary for the transmission of electrical signals.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: May 23, 2017
    Assignee: SANMINA CORPORATION
    Inventors: Douglas Ward Thomas, Shinichi Iketani
  • Publication number: 20150208514
    Abstract: The present invention relates to printed circuit boards (PCBs), and more particularly, to methods of forming high aspect ratio through holes and high precision stub removal in a printed circuit board (PCB). The high precision stub removal processes may be utilized in removing long stubs and short stubs. In the methods, multiple holes of varying diameter and depth are drilled from an upper and/or lower surface of the printed circuit board utilizing drills of different diameters.
    Type: Application
    Filed: January 22, 2015
    Publication date: July 23, 2015
    Inventors: Douglas Ward THOMAS, Shinichi IKETANI, Dale KERSTEN
  • Publication number: 20150047188
    Abstract: Cost effective and efficient methods to maximize printed circuit board (PCB) utilization with minimized signal degradation are provided. The methods include electrically isolating a segmented via structure by controlling the formation of a conductive material within a plated via structure by utilizing different diameter drills within a via structure for trimming the conductive material at the via shoulder (i.e., the rim of a drilled two diameter hole boundary). The trimmed portion may be voided in the via structure for allowing electrically isolated plated through-hole (PTH) segments. One or more areas of trimmed rims within the via structure are used to form multiple stair like diameter holes to create one or more voids in the via structure. As a result, the formation of conductive material within the via structure may be limited to those areas necessary for the transmission of electrical signals.
    Type: Application
    Filed: August 19, 2014
    Publication date: February 19, 2015
    Inventors: Douglas Ward Thomas, Shinichi Iketani