Abstract: Methods are provided for embedding auxiliary information in a host content signal which reduce the memory, bandwidth and computational complexity of the embedding and transmission systems. In one embodiment, a first reduced-scale signal is produced which corresponds to the host content embedded with a first logical value and producing a second reduced-scale signal corresponding to the host content embedded with a second logical value. A first set of segments from the first reduced-scale signal may be combined with a second set of segments from the second reduced-scale signal in a pre-defined manner to produce a composite embedded host content. Thus the storage and transmission requirements of the watermarking system are reduced to having to deal with only the original content plus two reduced-scale signals.

Abstract: An oversampled filter bank structure that can be implemented using popular and efficient fast filter banks to allow subband processing of an input signal with substantially reduced aliasing between subbands. Even subbands (SB0, SB2, SB4, . . . ) of an input signal (x(n)) are frequency-shifted (212, 1012, 1012?, 1012?) prior to analysis filtering (214, 214?, 214?) at a 2× oversampled filter bank, subband processing (240, 240?, 240?), and synthesis filtering (216, 216?, 216?). A subsequent frequency-shift (218, 218?) returns the even subbands to their original band positions. The odd subbands (SB1, SB3, SB5, . . . ) are delayed (252) to compensate for the processing time of the frequency shifting. Separate analysis (214, 214?) and synthesis (216, 216?) filter banks may be provided for the even and odd subbands, or common complex analysis (284) and synthesis (286) filter banks may be used. In another embodiment, the subbands are processed in four subband paths (Paths 0, 1, 2, 3), and 4× oversampling is used.

Abstract: Auxiliary information (150) representing binary or multi-level (M?2) logical values is embedded into successive segments (110) of an audio, video or other data signal in response to a user request to download the data signal via an on-line distributor (350) on a computer network such as the Internet. To avoid unnecessary delays in providing the data signal to the user, the data signal is pre-processed to provide two sets or copies of data (230, 235). One set (230) of the data contains segments with an embedded binary “0”, while the other set (235) contains corresponding segments with an embedded binary “1”. Successive segments are selected from one of the two sets to provide a time-multiplexed composite data signal (230) that has the desired content, but with an embedded binary data sequence that identifies the user.

Abstract: Auxiliary information (150) representing binary or multi-level (M?2) logical values is embedded into successive segments (110) of an audio, video or other data signal in response to a user request to download the data signal via an on-line distributor (350) on a computer network such as the Internet. To avoid unnecessary delays in providing the data signal to the user, the data signal is pre-processed to provide two sets or copies of data (230, 235). One set (230) of the data contains segments with an embedded binary “0”, while the other set (235) contains corresponding segments with an embedded binary “1”. Successive segments are selected from one of the two sets to provide a time-multiplexed composite data signal (230) that has the desired content, but with an embedded binary data sequence that identifies the user.

Abstract: A memory architecture allows for use of non-addressable NAND memory to be used as boot memory in digital processing systems. NAND memory, which is typically of lower cost and higher density, may displace all memory in processor systems, as particularly useful in low-power processor implementations. During commencement of a boot sequence, a preselected address is provided to a NAND flash memory. This preselected address coincides with that expected by a processor unit during commencement of a boot sequence. Upon completion of a selected duration, the NAND flash increments to a next, sequential memory location and thus outputs a sequence of instructions on its data lines. The data lines of the NAND flash memory are provided as input data lines to a processor unit. The processor unit, during a boot sequence, fetches subsequent boot instructions at a timing that coincides with that which is output from the NAND flash memory.