Abstract: A non-volatile memory device includes a first memory cell array, a first error correction code (ECC) decoder and a controller. The first memory cell array is divided into a first sub-array and a second sub-array by a first address boundary. The first ECC decoder is coupled to the first memory cell array, performs an ECC operation on read-out data from first memory cell array. The controller is coupled to the first memory cell array and the first ECC decoder, adjusts the first address boundary according to a first ECC failure bit number.

Abstract: A resistive memory with a self-termination control function and a self-termination control method for a resistive memory are provided. At least one memory cell comprises a cell transistor and a resistive element. A termination switch coupled to a source line terminates a write operation according to a comparison result. The comparator compares a voltage of a source line node with a reference voltage to output the comparison result, wherein the source line node is between the at least one memory cell and the termination switch, and the voltage of the source line node responses to the resistance of the resistive element. The variable resistance circuit provides an effective resistance according to a target resistance of the resistive element and outputs a reference current. The reference voltage node is coupled to the variable resistance circuit and the comparator and receives the reference current to provide the reference voltage to the comparator.

Abstract: The disclosure is directed to a RRAM having a plurality of 1TnR structures. In an aspect, the disclosure provides a RRAM including a plurality of 1TnR structures which includes a first 1TnR structure which includes a first transistor having a first gate terminal connected to a first word line, a first drain terminal, and a first source terminal connected to a source line, wherein the source line is connected to each of the plurality of 1TnR structures; and a first N parallel resistors group including a first resistor and a second resistor which are connected to the first drain terminal and connected to each other in parallel, wherein the first resistor is connected to a first bit line, the second resistor is connected to a second bit line, and N is an integer greater than one.

Abstract: A memory device and a method of assisting a read operation in the memory device are introduced. The memory device may include a logic circuit, a charge pump, a switch and a sense amplifier. The logic circuit is configured to receive at least one input signal and perform a logic operation on the at least one input signal to output an enable signal. The charge pump is coupled to the logic circuit and is configured to generate a boost voltage according to the enable signal. The switch is coupled between the charge pump and a sensing power supply line, and is configured to control an electrical connection between the charge pump and the sensing power supply line according to the enable signal to supply the boost voltage to the sensing power supply line. The sense amplifier is configured to perform a read operation using the boost voltage from the sensing power supply line.

Abstract: A PUF code generation apparatus that includes a reference generator, a PUF information generation and storage array, a sensing amplifier and a writing driver is introduced. The PUF information generation and storage array includes a plurality of first memory cells each including a PUF information providing element and a PUF information storage element. The sensing amplifier compares a plurality of first electrical values read from the PUF information providing elements to a reference generated from the reference generator to generate a plurality of PUF information. The writing driver performs a write-back operation on the PUF information storage elements according to the plurality of PUF information. The sensing amplifier reads a plurality of second electrical values of the PUF information storage elements to generate a sensing result and output a PUF code according to the sensing result.

Abstract: This disclosure introduces a programmable array logic (PAL) circuit and a method which are capable of preventing a read disturbance effect on memory cells of the PAL circuit. The PAL circuit comprises a memory array coupled to a plurality of input lines and a plurality of source lines, a plurality of input transition detection (ITD) circuits, a pulse generator and a plurality of sense amplifiers. The plurality of ITD circuits detect a transition in level of the plurality of input signals in the input lines. The pulse generator generates an enable signal according to the transition in level of the input signals. The sense amplifiers are enabled to sense the voltage levels of the source lines when the transition in levels of the input signals is detected, and the sense amplifiers are disabled when no transition in levels of the input signals is detected.

Abstract: This disclosure introduces a programmable array logic (PAL) circuit and a method which are capable of preventing a read disturbance effect on memory cells of the PAL circuit. The PAL circuit comprises a memory array coupled to a plurality of input lines and a plurality of source lines, a plurality of input transition detection (ITD) circuits, a pulse generator and a plurality of sense amplifiers. The plurality of ITD circuits detect a transition in level of the plurality of input signals in the input lines. The pulse generator generates an enable signal according to the transition in level of the input signals. The sense amplifiers are enabled to sense the voltage levels of the source lines when the transition in levels of the input signals is detected, and the sense amplifiers are disabled when no transition in levels of the input signals is detected.

Abstract: A data sensing apparatus adapted for sensing read-out data of a memory apparatus includes a sensing reference voltage generator, a sensing reference current generator, and a sense amplifier. The sensing reference voltage generator receives a reference voltage, generates a reference current according to the reference voltage and a control signal, and generates a sensing reference voltage according to the reference current. The sensing reference current generator receives the sensing reference voltage, and generates a sensing reference current according to the sensing reference voltage and the control signal. The sense amplifier receives the sensing reference current and a read-out current from the selected memory cell, and senses a current difference between the sensing reference current and the read-out current to generate the read-out data.

Abstract: A data sensing apparatus adapted for sensing read-out data of a memory apparatus includes a sensing reference voltage generator, a sensing reference current generator, and a sense amplifier. The sensing reference voltage generator receives a reference voltage, generates a reference current according to the reference voltage and a control signal, and generates a sensing reference voltage according to the reference current. The sensing reference current generator receives the sensing reference voltage, and generates a sensing reference current according to the sensing reference voltage and the control signal. The sense amplifier receives the sensing reference current and a read-out current from the selected memory cell, and senses a current difference between the sensing reference current and the read-out current to generate the read-out data.

Abstract: The invention provides a resistive memory apparatus including at least one first resistive memory cell, a first bit line selecting switch, a first source line selecting switch, a first pull down switch and a second pull down switch. The first bit line selecting switch is coupled between a first bit line and a sense amplifier. The first source line selecting switch is coupled between a source line and the sense amplifier. The first and second pull down switches are respectively coupled to the bit line and source line. When a reading operation is operated, on or off statuses of the first bit line selecting switch and the second pull down switch are the same, on or off statuses of the first source line selecting switch and the first pull down switch are the same, and on or off statuses of the first and second pull down switches are complementary.

Abstract: A resistive memory apparatus and a memory cell thereof are provided. The resistive memory cell includes a first transistor, a second transistor, a first resistor and a second resistor. First and second terminals of the first transistor are respectively coupled to a first bit line and a reference voltage. First and second terminals of the second transistor are respectively coupled to a second bit line and the reference voltage. The first resistor is serially coupled on a coupling path between the first terminal of the first transistor and the first bit line, or on a coupling path between the second terminal of the first transistor and the reference voltage. The second resistor is serially coupled on a coupling path between the first terminal of the second transistor coupled and the second bit line, or on a coupling path between the second terminal of the second transistor and the reference voltage.

Abstract: A resistive memory device is provided. A first cell is coupled to a word line, a first bit line and a source line. A second cell is coupled to the word line, a second bit line and the source line. A control circuit controls the levels of the word line, the first bit line and the source line to execute a set operation for the first cell and execute a reset operation for the second cell. After the set and the reset operations, the resistance of the first cell is less than the resistance of the second cell. During the execution of the set operation, the control circuit asserts the level of the source line at a pre-determined level. During the execution of the reset operation, the control circuit asserts the level of the source line at the pre-determined level.

Abstract: A resistive random-access memory (RRAM) device and a method thereof are disclosed. The RRAM device is contains a plurality of bit cells, a plurality of word lines, a plurality of bit lines and a plurality of source lines. Each bit cell includes a transistor and resistive element, the transistor includes a gate, a source and a drain, and the resistive element is coupled to the drain of the transistor. The plurality of word lines are arranged in parallel to one another, and coupled to respective gates of the transistors. The plurality of bit lines are arranged in parallel to one another and being intersected with the plurality of word lines, and coupled to respective drains of the transistors through the resistive elements. The plurality of source lines are arranged in parallel to one another and the plurality of bit lines.

Abstract: A resistive random-access memory (RRAM) device and a method thereof are disclosed. The RRAM device is contains a plurality of bit cells, a plurality of word lines, a plurality of bit lines and a plurality of source lines. Each bit cell includes a transistor and resistive element, the transistor includes a gate, a source and a drain, and the resistive element is coupled to the drain of the transistor. The plurality of word lines are arranged in parallel to one another, and coupled to respective gates of the transistors. The plurality of bit lines are arranged in parallel to one another and being intersected with the plurality of word lines, and coupled to respective drains of the transistors through the resistive elements. The plurality of source lines are arranged in parallel to one another and the plurality of bit lines.

Abstract: An RRAM circuit includes word lines, bit lines, source lines, memory cells, and a sense module. Each of the memory cells includes a resistor and a transistor. The resistor alternates between a high impedance and a low impedance, and is coupled to one of the bit lines. The transistor is controlled by one of the word lines and coupled between the resistor and one of the source lines. The sense module includes a switch and a sense amplifier. The switch is controlled by an output signal and coupled to one of the bit lines. The sense amplifier compares the data voltage, which is generated by a current flowing through the switch and the resistor, and a reference voltage to generate the output signal. The switch is turned off when the data voltage exceeds the reference voltage, and is turned on otherwise.

Abstract: A resistive memory apparatus and a memory cell thereof are provided. The resistive memory cell includes a first transistor, a second transistor, a first resistor and a second resistor. First and second terminals of the first transistor are respectively coupled to a first bit line and a reference voltage. First and second terminals of the second transistor are respectively coupled to a second bit line and the reference voltage. The first resistor is serially coupled on a coupling path between the first terminal of the first transistor and the first bit line, or on a coupling path between the second terminal of the first transistor and the reference voltage. The second resistor is serially coupled on a coupling path between the first terminal of the second transistor coupled and the second bit line, or on a coupling path between the second terminal of the second transistor and the reference voltage.

Abstract: A memory circuit includes at least one memory cell for storing a charge representative of a datum. The memory cell is coupled with a word line and a first bit line. At least one bit line equalization transistor is coupled between the first bit line and a second bit line. A bit line equalization circuit is coupled with the bit line equalization transistor. The bit line equalization circuit is configured for providing a pulse to the bit line equalization transistor to substantially equalize voltages of the first bit line and the second bit line during a standby period before an access cycle of the memory cell.

Abstract: A memory circuit includes at least one memory cell for storing a charge representative of a datum. The memory cell is coupled with a word line and a first bit line. At least one bit line equalization transistor is coupled between the first bit line and a second bit line. A bit line equalization circuit is coupled with the bit line equalization transistor. The bit line equalization circuit is configured for providing a pulse to the bit line equalization transistor to substantially equalize voltages of the first bit line and the second bit line during a standby period before an access cycle of the memory cell.

Abstract: A bit line sense-amplifier for a semiconductor memory device and a method for driving the same do not apply a bit line precharge voltage by a switch in an equalization operation, perform an equalization operation by interconnecting a plurality of sense-amplifier lines, then perform a precharge operation by applying a bit line precharge voltage through NMOS transistor of the switch, increase a sensing speed by reducing a loading of a sense-amplifier, reduce a transient current, and minimize a power-consumption by performing a precharge operation after a bit line equalization.

Abstract: A SRAM device according to the present invention performs a stable data latch operation. The present invention provides a negative voltage generator which is coupled to the drive transistors in the SRAM device for providing negative voltage for the drive transistors during a read cycle of the SRAM device when a word line of the SRAM device is activated. The negative voltage generator includes an output terminal coupled to access transistors, a current path for discharging the output terminal up to a ground voltage level in response to control signals, and a pump for pumping the output terminal to make the output terminal be in a negative voltage level.