Patents by Inventor Doulgas W. Barlage

Doulgas W. Barlage has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Silicon-on-insulator structure and method of reducing backside drain-induced barrier lowering
    Patent number: 6873013
    Abstract: The invention relates to a transistor that includes a semiconductive layer on an insulator layer. Below the insulator layer is a substrate and a contact is disposed in the insulator layer that originates at the substrate and terminates in the insulator layer. The contact is aligned below the transistor junction. The invention also relates to a process flow that is used to fabricate the transistor. The process flow includes forming the contact by either a spacer etch or a directional, angular etch.
    Type: Grant
    Filed: March 24, 2003
    Date of Patent: March 29, 2005
    Assignee: Intel Corporation
    Inventors: Brian Roberds, Doulgas W. Barlage
  • Silicon-on-insulator structure and method of reducing backside drain-induced barrier lowering
    Patent number: 6642133
    Abstract: The invention relates to a transistor that includes a semiconductive layer on an insulator layer. Below the insulator layer is a substrate and a contact is disposed in the insulator layer that originates at the substrate and terminates in the insulator layer. The contact is aligned below the transistor junction. The invention also relates to a process flow that is used to fabricate the transistor. The process flow includes forming the contact by either a spacer etch or a directional, angular etch.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: November 4, 2003
    Assignee: Intel Corporation
    Inventors: Brian Roberds, Doulgas W. Barlage
  • Silicon-on-insulator structure and method of reducing backside drain-induced barrier lowering
    Publication number: 20030178680
    Abstract: The invention relates to a transistor that includes a semiconductive layer on an insulator layer. Below the insulator layer is a substrate and a contact is disposed in the insulator layer that originates at the substrate and terminates in the insulator layer. The contact is aligned below the transistor junction. The invention also relates to a process flow that is used to fabricate the transistor. The process flow includes forming the contact by either a spacer etch or a directional, angular etch.
    Type: Application
    Filed: March 24, 2003
    Publication date: September 25, 2003
    Inventors: Brian Roberds, Doulgas W. Barlage
  • Silicon-on-insulator structure and method of reducing backside drain-induced barrier lowering
    Publication number: 20030116812
    Abstract: The invention relates to a transistor that includes a semiconductive layer on an insulator layer. Below the insulator layer is a substrate and a contact is disposed in the insulator layer that originates at the substrate and terminates in the insulator layer. The contact is aligned below the transistor junction. The invention also relates to a process flow that is used to fabricate the transistor. The process flow includes forming the contact by either a spacer etch or a directional, angular etch.
    Type: Application
    Filed: December 20, 2001
    Publication date: June 26, 2003
    Applicant: Intel Corporation
    Inventors: Brian Roberds, Doulgas W. Barlage