Abstract: An improved architecture for and a method of operating a high speed synchronous state machine is disclosed having a programmable logic array receiving inputs from dedicated input registers and having an input/output macrocell which includes two state registers and two input registers, and two transparent latches and two feedback multiplexers. The outputs from the input registers are multiplexed through an input multiplexer and the input registers may be clocked at different input clock rates than the state clock which clocks the state registers.

Abstract: Apparatus for controlling the programming voltage of an EPROM array composed of a plurality of programmable floating gate MOS cells, which includes an additional floating gate MOS cell fabricated on the same chip and in the same manner as the array of cells, the additional cell not being connected for programming during the normal programming of the array. A voltage is applied to the additional cell to generate a drain current through the cell. A feedback control is connected between the source of external programming voltage for the array and the actual voltage within the array used for programming the cells, the feedback control using the amplitude of the drain current in the additional cell to control the magnitude of the actual programming voltage in the array in such a manner that when the drain current of the additional cell increases, the programming voltage decreases proportionately.

Abstract: An improved architecture for and a method of operating a high speed synchronous state machine is disclosed having a programmable logic array receiving inputs from dedicated input registers and having an input/output macrocell which includes two state registers and two input registers, and two transparent latches and two feedback multiplexers. The outputs from the input registers are multiplexed through an input multiplexer and the input registers may be clocked at different input clock rates than the state clock which clocks the state registers.

Abstract: The invention pertains to a circuit for controlling the power to a plurality of sense amplifiers used for sensing data on data lines in an array of floating gate storage cells, wherein the data stored in the array is sensed at regular intervals. The circuit includes a first plurality of data paths through the array, and a second data path containing replications of all necessary circuit elements in the first plurality of data paths to assure that the data delay through the second path equals or exceeds the maximum delay in any of the first plurality of data paths. A clock is used to provide an initiation signal which starts the propagation of input data through the array. A means is coupled to the clock for sending a dummy data pulse through the second data path upon receipt of the initiation signal, and a detecting means detects the completion of the passage of the dummy data through the second path and supplies a completion signal in response.