Abstract: Reducing turn around time of engineering change orders in ASIC re-spin design includes finding, on the fly, all corresponding boundary points of storage gate elements indicated by engineering change orders to be either added, deleted or renamed. Boolean equivalence tools are used between an old spin ASIC design and a new ASIC design netlist, as well as between the new ASIC design netlist and a new re-spin ASIC design to obtain failing boundary storage gate elements and perform one or more of adding, deleting or modifying or renaming all failing boundary storage gate elements, so they pass correspondence tests. Engineering change order scripts are automatically generated to indicate which storage logic gate elements are to be added, deleted or modified and the scripts are applied to the old ASIC design to obtain the new re-spin ASIC design, after which ASIC flow gate level fixes are applied to synthesized storage gate elements.