Abstract: A first storage location at a memory management unit stores physical address information mapping logical physical addresses to actual physical addresses. A second storage location stores an allowed address range of actual physical addresses. A memory management unit determines whether a write access to the first storage location is allowable. The access is to store memory mapping information relating to a first actual physical address. The memory management unit prevents the write access if the first actual physical address is not in the allowed address range, and does not prevent the write access if the first actual physical address is in the allowed address range. The memory management unit prevents a write access to the second storage location by a process that is not running in a hypervisor mode.

Abstract: A first storage location at a memory management unit stores physical address information mapping logical physical addresses to actual physical addresses. A second storage location stores an allowed address range of actual physical addresses. A memory management unit determines whether a write access to the first storage location is allowable. The access is to store memory mapping information relating to a first actual physical address. The memory management unit prevents the write access if the first actual physical address is not in the allowed address range, and does not prevent the write access if the first actual physical address is in the allowed address range. The memory management unit prevents a write access to the second storage location by a process that is not running in a hypervisor mode.

Abstract: A system, computer program and a method for debugging a system, the method includes: controlling, by a debugger, an execution flow of a processing entity; setting, by the debugger or the processing entity, a value of a scheduler control variable accessible by the scheduler; wherein the debugger is prevented from directly controlling an execution flow of a scheduler; and determining, by the scheduler, an execution flow of the scheduler in response to a value of the scheduler control variable.

Abstract: The invention pertains to a memory management unit for a microprocessor system, the memory management unit being connected or connectable to at least one processor core of the microprocessor system and being connected or connectable to a physical memory of the microprocessor system. The memory management unit is adapted to selectively operate in a hypervisor mode or in a supervisor mode, the hypervisor mode and the supervisor mode having different privilege levels of access to hardware The memory management unit comprises a first register table indicating physical address information for mapping at least one logical physical address and at least one actual physical address onto each other; a second register table indicating an allowed address range of physical addresses accessible to a process running in or under supervisor mode; wherein the memory management unit is adapted to prevent write access to the second register table by a process not in hypervisor mode.

Abstract: A system, computer program and a method for scheduling a processing entity task in a multiple-processing entity system, the method includes initializing a scheduler; receiving a task data structure indicative that a pre-requisite to an execution of task to be executed by a processing entity is a completion of a peripheral task that is executed by a peripheral; wherein the peripheral updates a peripheral task completion indicator once the peripheral task is completed; wherein the peripheral task completion indicator is accessible by the scheduler; and scheduling, by the scheduler, the task in response to the peripheral task completion indicator.

Abstract: A system, computer program and a method for preventing starvations of tasks in a multiple-processing entity system, the method includes: examining, during each scheduling iteration, an eligibility of each task data structure out of a group of data structures to be moved from a sorted tasks queue to a ready for execution task; updating a value, during each scheduling iteration, of a queue starvation watermark value of each task data structure that is not eligible to move to a running tasks queue, until a queue starvation watermark value of a certain task data structure out of the group reaches a queue starvation watermark threshold; and generating a task starvation indication if during an additional number of scheduling iterations, the certain task data structure is still prevented from being moved to a running tasks queue, and the additional number is responsive to a task starvation watermark.

Abstract: The invention pertains to a memory management unit for a microprocessor system, the memory management unit being connected or connectable to at least one processor core of the microprocessor system and being connected or connectable to a physical memory of the microprocessor system. The memory management unit is adapted to selectively operate in a hypervisor mode or in a supervisor mode, the hypervisor mode and the supervisor mode having different privilege levels of access to hardware The memory management unit comprises a first register table indicating physical address information for mapping at least one logical physical address and at least one actual physical address onto each other; a second register table indicating an allowed address range of physical addresses accessible to a process running in or under supervisor mode; wherein the memory management unit is adapted to prevent write access to the second register table by a process not in hypervisor mode.

Abstract: A method for locating an end of a received frame includes providing hypothetical trellis paths that end at different possible end points, performing a CRC check for each hypothetical trellis path, calculating a false detection variable for hypothetical trellis paths that passed the CRC check, and determining the end point of the received frame in response to the calculations.

Abstract: A system, computer program and a method for debugging a system, the method includes: controlling, by a debugger, an execution flow of a processing entity; setting, by the debugger or the processing entity, a value of a scheduler control variable accessible by the scheduler; wherein the debugger is prevented from directly controlling an execution flow of a scheduler; and determining, by the scheduler, an execution flow of the scheduler in response to a value of the scheduler control variable.

Abstract: A system, computer program and a method, the method for scheduling processor entity tasks in a multiple-processing entity system includes: receiving task data structures from multiple processing entities; wherein a task data structure represents a task to be executed by a processing entity; and scheduling an execution of the tasks by a multiple purpose entity.

Abstract: A system, computer program and a method for scheduling a processing entity task in a multiple-processing entity system, the method includes initializing a scheduler; receiving a task data structure indicative that a pre-requisite to an execution of task to be executed by a processing entity is a completion of a peripheral task that is executed by a peripheral; wherein the peripheral updates a peripheral task completion indicator once the peripheral task is completed; wherein the peripheral task completion indicator is accessible by the scheduler; and scheduling, by the scheduler, the task in response to the peripheral task completion indicator.

Abstract: A device (100) for locating an end of a received frame, the device comprises: at least one memory unit (120) for storing path metrics; at least one processor, adapted to: provide hypothetical trellis paths that end at different possible end points; perform, for each hypothetical trellis path, a forward detection check; calculate a false detection variable for hypothetical trellis paths that passed the forward check; and determine the end point of the received frame in response to the calculations. Wherein the calculation of the forward detection check is much faster than the calculation of the false detection variable.

Abstract: A system, computer program and a method for preventing starvations of tasks in a multiple-processing entity system, the method includes: examining, during each scheduling iteration, an eligibility of each task data structure out of a group of data structures to be moved from a sorted tasks queue to a ready for execution task; updating a value, during each scheduling iteration, of a queue starvation watermark value of each task data structure that is not eligible to move to a running tasks queue, until a queue starvation watermark value of a certain task data structure out of the group reaches a queue starvation watermark threshold; and generating a task starvation indication if during an additional number of scheduling iterations, the certain task data structure is still prevented from being moved to a running tasks queue, wherein the additional number is responsive to a task starvation watermark.