Patents by Inventor Doyle Rivers
Doyle Rivers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10936418Abstract: Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.Type: GrantFiled: June 18, 2019Date of Patent: March 2, 2021Assignee: Intel CorporationInventors: Kiran Pangal, Prashant S. Damle, Rajesh Sundaram, Shekoufeh Qawami, Julie M. Walker, Doyle Rivers
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Patent number: 10678315Abstract: Data reliability and integrity may be compromised when memory resources used to store the data reach elevated temperatures. A sensor in the memory resource may monitor the temperature of the memory resource in real-time. A comparator in the memory resource may indicate a high temperature condition to a memory controller. The memory controller, in response to the high temperature condition, can restrict or halt data flow to the memory resource. When the real-time temperature of the memory resource falls below a defined threshold, the memory controller may resume data flow to the memory resource.Type: GrantFiled: October 1, 2018Date of Patent: June 9, 2020Assignee: Intel CorporationInventors: Rajesh Sundaram, Muthukumar P. Swaminathan, Doyle Rivers
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Publication number: 20190370112Abstract: Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.Type: ApplicationFiled: June 18, 2019Publication date: December 5, 2019Inventors: Kiran PANGAL, Prashant S. DAMLE, Rajesh SUNDARAM, Shekoufeh QAWAMI, Julie M. WALKER, Doyle RIVERS
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Patent number: 10325652Abstract: Technology for verifying cell programming for a phase change memory array is disclosed. In an example, a method may include sending a reset pulse to a phase change memory cell. The method may further include sensing a threshold voltage of the phase change memory cell in response to applying first and second verify voltages across the phase change memory cell, where the second verify voltage is lower than the first verify voltage. The method may also include determining whether the threshold voltage of the phase change memory cell was below the first or second verify voltages.Type: GrantFiled: August 29, 2017Date of Patent: June 18, 2019Assignee: Intel CorporationInventors: Daniel J. Chu, Raymond W. Zeng, Doyle Rivers
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Patent number: 10324793Abstract: Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.Type: GrantFiled: March 1, 2018Date of Patent: June 18, 2019Assignee: Intel CorporationInventors: Kiran Pangal, Prashant S. Damle, Rajesh Sundaram, Shekoufeh Qawami, Julie M. Walker, Doyle Rivers
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Patent number: 10289597Abstract: Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.Type: GrantFiled: May 9, 2018Date of Patent: May 14, 2019Assignee: Micron Technology, Inc.Inventors: Doyle Rivers, Paul D. Ruby, Anand S. Ramalingam, Rajesh Sundaram, Julie M. Walker
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Publication number: 20190107871Abstract: Data reliability and integrity may be compromised when memory resources used to store the data reach elevated temperatures. A sensor in the memory resource may monitor the temperature of the memory resource in real-time. A comparator in the memory resource may indicate a high temperature condition to a memory controller. The memory controller, in response to the high temperature condition, can restrict or halt data flow to the memory resource. When the real-time temperature of the memory resource falls below a defined threshold, the memory controller may resume data flow to the memory resource.Type: ApplicationFiled: October 1, 2018Publication date: April 11, 2019Applicant: Intel CorporationInventors: RAJESH SUNDARAM, MUTHUKUMAR P. SWAMINATHAN, DOYLE RIVERS
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Publication number: 20180329854Abstract: Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.Type: ApplicationFiled: May 9, 2018Publication date: November 15, 2018Inventors: Doyle Rivers, Paul D. Ruby, Anand S. Ramalingam, Rajesh Sundaram, Julie M. Walker
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Patent number: 10088880Abstract: Data reliability and integrity may be compromised when memory resources used to store the data reach elevated temperatures. A sensor in the memory resource may monitor the temperature of the memory resource in real-time. A comparator in the memory resource may indicate a high temperature condition to a memory controller. The memory controller, in response to the high temperature condition, can restrict or halt data flow to the memory resource. When the real-time temperature of the memory resource falls below a defined threshold, the memory controller may resume data flow to the memory resource.Type: GrantFiled: August 27, 2015Date of Patent: October 2, 2018Assignee: Intel CorporationInventors: Rajesh Sundaram, Muthukumar P. Swaminathan, Doyle Rivers
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Publication number: 20180253355Abstract: Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.Type: ApplicationFiled: March 1, 2018Publication date: September 6, 2018Inventors: Kiran PANGAL, Prashant S. DAMLE, Rajesh SUNDARAM, Shekoufeh QAWAMI, Julie M. WALKER, Doyle RIVERS
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Patent number: 10062444Abstract: An integrated circuit, that may be a part of an electronic system, may include a first set of storage cells to store settings and a second set of storage cells to store alternate settings. At least one control cell may also be included in the integrated circuit. The at least one control cell may indicate whether to use the settings stored in the first set of storage cells, or the alternate settings stored in the second set of storage cells, to control one or more operating parameters of the integrated circuit. Methods for using the alternate setting are also described.Type: GrantFiled: February 8, 2016Date of Patent: August 28, 2018Assignee: Intel CorporationInventors: Julie M. Walker, Doyle Rivers
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Patent number: 10056139Abstract: Apparatus, systems, and methods to correct for threshold voltage drift in non-volatile memory devices are disclosed and described. In one example, a compensated demarcation voltage is generated by either a time-based drift compensation scheme or a disturb-based drift compensation scheme, and read and write operations to the non-volatile memory are carried out using the compensated voltage threshold.Type: GrantFiled: July 10, 2017Date of Patent: August 21, 2018Assignee: Intel CorporationInventors: Shekoufeh Qawami, Rajesh Sundaram, Prashant S. Damle, Doyle Rivers, Julie M. Walker
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Patent number: 9996496Abstract: Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.Type: GrantFiled: August 24, 2017Date of Patent: June 12, 2018Assignee: Micron Technology, Inc.Inventors: Doyle Rivers, Paul D. Ruby, Anand S. Ramalingam, Rajesh Sundaram, Julie M. Walker
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Patent number: 9934088Abstract: Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.Type: GrantFiled: September 3, 2015Date of Patent: April 3, 2018Assignee: Intel CorporationInventors: Kiran Pangal, Prashant S. Damle, Rajesh Sundaram, Shekoufeh Qawami, Julie M. Walker, Doyle Rivers
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Publication number: 20180068720Abstract: Technology for verifying cell programming for a phase change memory array is disclosed. In an example, a method may include sending a reset pulse to a phase change memory cell. The method may further include sensing a threshold voltage of the phase change memory cell in response to applying first and second verify voltages across the phase change memory cell, where the second verify voltage is lower than the first verify voltage. The method may also include determining whether the threshold voltage of the phase change memory cell was below the first or second verify voltages.Type: ApplicationFiled: August 29, 2017Publication date: March 8, 2018Applicant: Intel CorporationInventors: Daniel J. Chu, Raymond W. Zeng, Doyle Rivers
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Publication number: 20170372780Abstract: Apparatus, systems, and methods to correct for threshold voltage drift in non-volatile memory devices are disclosed and described. In one example, a compensated demarcation voltage is generated by either a time-based drift compensation scheme or a disturb-based drift compensation scheme, and read and write operations to the non-volatile memory are carried out using the compensated voltage threshold.Type: ApplicationFiled: July 10, 2017Publication date: December 28, 2017Applicant: Intel CorporationInventors: Shekoufeh Qawami, Rajesh Sundaram, Prashant S. Damle, Doyle Rivers, Julie M. Walker
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Publication number: 20170351637Abstract: Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.Type: ApplicationFiled: August 24, 2017Publication date: December 7, 2017Inventors: Doyle Rivers, Paul D. Ruby, Anand S. Ramalingam, Rajesh Sundaram, Julie M. Walker
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Patent number: 9785603Abstract: Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.Type: GrantFiled: July 18, 2016Date of Patent: October 10, 2017Assignee: Micron Technology, Inc.Inventors: Doyle Rivers, Paul D. Ruby, Anand S. Ramalingam, Rajesh Sundaram, Julie M. Walker
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Patent number: 9747977Abstract: Technology for verifying cell programming for a phase change memory array is disclosed. In an example, a method may include sending a reset pulse to a phase change memory cell. The method may further include sensing a threshold voltage of the phase change memory cell in response to applying first and second verify voltages across the phase change memory cell, where the second verify voltage is lower than the first verify voltage. The method may also include determining whether the threshold voltage of the phase change memory cell was below the first or second verify voltages.Type: GrantFiled: March 14, 2013Date of Patent: August 29, 2017Assignee: INTEL CORPORATIONInventors: Daniel J. Chu, Raymond W. Zeng, Doyle Rivers
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Patent number: 9747978Abstract: The present disclosure relates to reference and sense architecture in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes word line (WL) switch circuitry configured to select a global WL (GWL) and a local WL (LWL) associated with the target memory cell; bit line (BL) switch circuitry configured to select a global BL (GBL) and a local BL (LBL) associated with the target memory cell; and sense circuitry including a first sense circuitry capacitance and a second sense circuitry capacitance, the sense circuitry configured to precharge the selected GWL, the LWL and the first sense circuitry capacitance to a WL bias voltage WLVDM, produce a reference voltage (VREF) utilizing charge on the selected GWL and charge on the first sense circuitry capacitance and determine a state of the target memory cell based, at least in part, on VREF and a detected memory cell voltage VLWL.Type: GrantFiled: September 10, 2015Date of Patent: August 29, 2017Assignee: INTEL CORPORATIONInventors: Balaji Srinivasan, Doyle Rivers, Derchang Kau, Matthew Goldman