Abstract: A state machine in which the next state signals are biased by the next state encoder very close to the switch voltage of the input transistors of the present state latches to improve the response time of the state machine. Charge sharing on the outputs of the next state selector is prevented from affecting the biased next state signals by voltage substaining circuitry. By pre-encoding input signals pertinent to each state using separate input logic, the size of the next state selector is minimized, further improving the response time of the state machine. Selected present state latches may be prevented from changing state by gating the next state signals.

Abstract: A buffer circuit is provided for buffering an input clock signal having TTL voltage levels to provide an output clock signal having MOS voltage levels. A reference voltage portion provides an accurate bias voltage to a first node. A voltage translation portion is coupled between an input and the first node. An inverter portion has a first input connected to the first node, a second input for receiving the input clock signal, and an output for providing the output clock signal. A clamping portion is connected to the first node to minimize the bias voltage potential.

Abstract: Each channel of a priority encoder register is equipped with a latch for storing one bit of a binary data word. The channel of highest priority generates an output which is applied to encoding means which in turn generates a unique code. The channel output is also fed back to reset its associated latch to permit the channel of next highest priority to generate an output.

Abstract: A read-only-memory circuit is disclosed which includes a plurality of column conductors and circuitry for selecting one of the plurality of column conductors in response to an input address. The selection circuitry couples each of the column conductors to a common node which is coupled to a precharge circuit such that only the selected column conductor is precharged. The precharged circuit includes first and second diode-connected IGFET devices coupled in series such that the first IGFET device is a standard enhancement mode transistor which includes an implanted channel while the second IGFET device is a natural transistor which does not include an implanted channel.

Abstract: A data processor having an execution unit employs a segmented bus structure and a dual port register cell in order to increase circuit density and in order to allow address and data computations to occur simultaneously. The circuit is designed to interface with an external 16-bit bidirectional data bus and an external address bus having as many as 32 address bits. Serial bus switches on each of two parallel buses allow concatenation with a second pair of buses. Each bus, while 16 bits wide, actually utilizes two conductors per bit to carry data and the complement thereof.

Abstract: A decoder circuit suitable for integrated circuit implementation using IGFET processing is disclosed which may be implemented in a highly dense structure. The decoder output lines are grouped in pairs and at least one of the output lines in each pair is discharged as determined by a bit in the input address. A plurality of IGFET devices under the control of the remaining input address bits selectively couple together the two output lines in each pair such that both output lines can then become discharged. Series-coupled pairs of IGFET devices are used in place of a single IGFET device in order to reduce the chip area required to implement the decoder structure.