Abstract: A method of etching high aspect ratio, anisotropic deep trench openings in a silicon substrate coated with a multilayer mask comprising in sequence a pad oxide layer, a silicon nitride layer, a doped or undoped silicon oxide hard mask layer, a polysilicon hard mask layer, an antireflection coating and a patterned photoresist layer in a single chamber comprising patterning the antireflection coating and hard mask layer, removing the photoresist and antireflection layers with oxygen, using the patterned polysilicon as a hard mask layer etching an opening in the silicon oxide hard mask layer, the silicon nitride layer and the pad oxide layer, removing the polysilicon hard mask layer with CF4/CHF3, and etching an anisotropic deep trench in the silicon substrate using the patterned silicon oxide hard mask layer as a mask and an etchant mixture including nitrogen trifluoride that self-cleans the chamber.

Abstract: A method and apparatus for selectively controlling a plasma in a processing chamber during wafer processing. The method includes providing process gasses into the chamber over a wafer to be processed, and providing high frequency RF power to a plasma generating element and igniting the process gases into the plasma. Modulated RF power is coupled to a biasing element, and wafer processing is performed according to a particular processing recipe. The apparatus includes a biasing element disposed in the chamber and adapted to support a wafer, and a plasma generating element disposed over the biasing element and wafer. A first power source is coupled to the plasma generating element, and a second power source is coupled to the biasing element. A third power source is coupled to the biasing element, wherein the second and third power sources provide a modulated signal to the biasing element.

Abstract: One embodiment of the present invention is an etching method for use in fabricating an integrated circuit device on a wafer or substrate in an inductively coupled plasma reactor in a passivation-driven etch chemistry, which method includes steps of: (a) providing a passivation-driven etch chemistry precursor in a chamber of the reactor wherein a first coil is disposed to supply energy primarily to an outer portion of the chamber and a second coil is disposed to supply energy primarily to an inner portion of the chamber; and (b) providing power to the first coil and the second coil in a ratio of power supplied to the first coil and power supplied to the second coil greater than 1.

Abstract: Processes for forming trenches within silicon substrates are described. According to an embodiment of the invention, a masked substrate is initially provided that comprises (a) a silicon substrate and (b) a patterned resist layer over the silicon substrate. The patterned resist layer has one or more apertures formed therein. Subsequently, a trench is formed in the substrate through the apertures in the resist layer by an inductive plasma-etching step, which is conducted using plasma source gases that comprise SF6, at least one fluorocarbon gas, and N2. If desired, Cl2 can also be provided in addition to the above source gases. The process of the present invention produces chamber deposits in low amounts, while providing high etching rates, high silicon:resist selectivities, and good trench sidewall profile control.

Abstract: A method and apparatus for dicing a semiconductor wafer using a plasma etch process. The method begins by applying a patterned mask to the integrated circuits on a wafer. The pattern covers the circuits and exposes the streets between the dice. Next, the method deposits a uniform layer of adhesive material upon a carrier wafer. The wafer to be diced is affixed to the carrier wafer via the adhesive material that is sandwiched between the bottom surface of the wafer to be diced and the top surface of the carrier wafer. The combination assembly of the carrier wafer, adhesive and wafer to be diced is placed in an etch reactor that is capable of etching silicon. When the reactive gas is applied to the combination assembly, the etch plasma will consume the unprotected silicon within the streets and dice the wafer into individual integrated circuit chips. The carrier wafer is then removed from the etch chamber with the dice still attached to the adhesive layer.

Abstract: A method for plasma etching substrates having high open area patterns is described. The method is useful in microelectrical mechanical system (MEMS) applications, and in the fabrication of integrated circuits and other electronic devices. The method can be used to etch strict profile control trenches with 89° +/−1° sidewalls on silicon substrates with high open area patterns such as patterns between about 50% and about 90%. The novel method plasma etches high open area substrates using a plasma formed from a gaseous mixture that includes an oxygen source gas, a fluorine source gas and a fluorocarbon source gas. In an alternative embodiment, the fluorocarbon source gas is a passivation gas. In another alternative embodiment, the fluorocarbon source gas consists essentially of a fluorocarbon having fluorine and carbon in a 2:1 ratio. In another particular embodiment, the oxygen source gas is O2, the fluorine source gas is SF6 and the fluorocarbon source gas is C4F8.

Abstract: A method of etching high aspect ratio, anisotropic deep trench openings in a silicon substrate coated with a multilayer mask comprising in sequence a pad oxide layer, a silicon nitride layer, a doped or undoped silicon oxide hard mask layer, a polysilicon hard mask layer, an antireflection coating and a patterned photoresist layer in a single chamber comprising patterning the antireflection coating and hard mask layer, removing the photoresist and antireflection layers with oxygen, using the patterned polysilicon as a hard mask layer etching an opening in the silicon oxide hard mask layer, the silicon nitride layer and the pad oxide layer, removing the polysilicon hard mask layer with CF4/CHF3, and etching an anisotropic deep trench in the silicon substrate using the patterned silicon oxide hard mask layer as a mask and an etchant mixture including nitrogen trifluoride that self-cleans the chamber.

Abstract: A method and apparatus for dicing a semiconductor wafer using a plasma etch process. The method begins by applying a patterned mask to the integrated circuits on a wafer. The pattern covers the circuits and exposes the streets between the dice. Next, the method deposits a uniform layer of adhesive material upon a carrier wafer. The wafer to be diced is affixed to the carrier wafer via the adhesive material that is sandwiched between the bottom surface of the wafer to be diced and the top surface of the carrier wafer. The combination assembly of the carrier wafer, adhesive and wafer to be diced is placed in an etch reactor that is capable of etching silicon. When the reactive gas is applied to the combination assembly, the etch plasma will consume the unprotected silicon within the streets and dice the wafer into individual integrated circuit chips. The carrier wafer is then removed from the etch chamber with the dice still attached to the adhesive layer.

Abstract: Processes for forming trenches within silicon substrates are described. According to an embodiment of the invention, a masked substrate is initially provided that comprises (a) a silicon substrate and (b) a patterned resist layer over the silicon substrate. The patterned resist layer has one or more apertures formed therein. Subsequently, a trench is formed in the substrate through the apertures in the resist layer by an inductive plasma-etching step, which is conducted using plasma source gases that comprise SF6, at least one fluorocarbon gas, and N2. If desired, Cl2 can also be provided in addition to the above source gases. The process of the present invention produces chamber deposits in low amounts, while providing high etching rates, high silicon:resist selectivities, and good trench sidewall profile control.

Abstract: This invention is directed to a method for rapid plasma etching of materials which are difficult to etch at a high rate. The method is particularly useful in plasma etching silicon nitride layers more than five microns thick. The method includes the use of a plasma source gas that includes an etchant gas and a sputtering gas. Two separate power sources are used in the etching process and the power to each power source as well as the ratio between the flow rates of the etchant gas and sputtering gas can be advantageously adjusted to obtain etch rates of silicon nitride greater than two microns per minute. Additionally, an embodiment of the method of the invention provides a two etch step process which combines a high etch rate process with a low etch rate process to achieve high throughput while minimizing the likelihood of damage to underlying layers. The first etch step of the two-step method provides a high etch rate of about two microns per minute to remove substantially all of a layer to be etched.

Abstract: A method for controlling a profile of a structure formed on a substrate using nitrogen trifluoride (NF3) in a high density plasma (HDP) process. Changing the amount of NF3 in the plasma controls the profile of the structure. It has been found that the best results are obtained with an inductively coupled plasma wherein the ion density is at least 1012 ions/cm3. The method is particularly suited to etch processes such as deep trench etch in silicon wafers.

Abstract: This invention is directed to a method for plasma etching difficult to etch materials at a high etch rate. The method is particularly useful in plasma etching silicon nitride layers more than five microns thick. The method includes a plasma formed by energy provided from two separate power sources and a gaseous mixture that includes only an etchant gas and a sputtering gas. The power levels from the separate power sources and the ratio between the flow rates of the etchant gas and a sputtering gas can be advantageously adjusted to obtain etch rates of silicon nitride greater than two microns per minute. Additionally, an embodiment of the method of the invention provides a two etch step process which combines a high etch rate process with a low etch rate process to achieve high throughput while minimizing the likelihood of damage to underlying layers. The first etch step of the two-step method provides a high etch rate of about two microns per minute to remove substantially all of a layer to be etched the.

Abstract: The sensitivity of localized photochemical etching to the optical and electrical properties of multilayered semiconductor materials is utilized for selectively etching a laterally extending undercut in a buried layer. The semiconductor body is immersed in a suitable etching solution and a beam of light of appropriate wavelength and intensity is directed onto the semiconductor solution interface. The buried layer has a longer diffusion length for photogenerated carriers than the layers adjacent thereto, casuing carriers to diffuse away from the illuminated region within the buried layer and thereby etch the buried layer laterally, undercutting the adjacent layers.