Abstract: In an embodiment a system on chip includes a plurality of microprocessors, a plurality of slave resources, an interconnection circuit coupled between the microprocessors and the slave resources, the interconnection circuit configured to route transactions between the microprocessors and the slave resources and a processing controller configured to allow a user of the system to implement within the system at least one configuration diagram of the system defined by a set of configuration pieces of information used to define an assignment of at least one microprocessor to at least some of the slave resources, select the at least one microprocessors, and authorise an external debugging tool to access, for debugging purposes, only the slave resources assigned to the at least one microprocessor.

Abstract: A system for determining context and intent in a conversation using machine learning (ML) based artificial intelligence (AI) in omnichannel data communications is disclosed. The system may comprise a data store to store and manage data within a network, a server to facilitate operations using information from the one or more data stores, and a ML-based AI subsystem to communicate with the server and the data store in the network. The ML-based AI subsystem may comprise a data access interface to receive data associated with a conversation with a user via a communication channel. The ML-based AI subsystem may comprise a processor to provide a proactive, adaptive, and intelligent conversation by applying hierarchical multi-intent data labeling framework, training at least one model with training data, and generating and deploying a production-ready model based on the trained and retained at least one model.

Abstract: In an embodiment a system on chip includes a plurality of microprocessors, a plurality of slave resources, an interconnection circuit coupled between the microprocessors and the slave resources, the interconnection circuit configured to route transactions between the microprocessors and the slave resources and a processing controller configured to allow a user of the system to implement within the system at least one configuration diagram of the system defined by a set of configuration pieces of information used to define an assignment of at least one microprocessor to at least some of the slave resources, select the at least one microprocessors, and authorise an external debugging tool to access, for debugging purposes, only the slave resources assigned to the at least one microprocessor.

Abstract: A system for determining context and intent in a conversation using machine learning (ML) based artificial intelligence (AI) in omnichannel data communications is disclosed. The system may comprise a data store to store and manage data within a network, a server to facilitate operations using information from the one or more data stores, and a ML-based AI subsystem to communicate with the server and the data store in the network. The ML-based AI subsystem may comprise a data access interface to receive data associated with a conversation with a user via a communication channel. The ML-based AI subsystem may comprise a processor to provide a proactive, adaptive, and intelligent conversation by applying hierarchical multi-intent data labeling framework, training at least one model with training data, and generating and deploying a production-ready model based on the trained and retained at least one model.

Abstract: An embodiment system includes a first processor configured to process a suite of instructions and a second processor configured to process a subset of the suite of instructions. The system further includes a power management circuit configured to select the first processor or the second processor as a selected processor, the power management circuit being further configured to activate the selected processor or place the selected processor on standby. The system also includes a first peripheral device configured to generate a first interrupt signal, a switch configured to direct the first interrupt signal to the selected processor, and a first memory configured to store a first interrupt routine associated with the first interrupt signal, the selected processor being configured to execute the first interrupt routine in response to the first interrupt signal.

Abstract: A memory access control system includes a first circuit supporting direct access to the memory and a second circuit that is associated with the first circuit and programmed to restrict an area of the memory that is accessible to the first circuit. A central processing unit operates in privileged mode to program the second circuit with a range of addresses within the memory where read and write operations are permitted and further operates in limited mode to program the first circuit with a starting address for read and write operations associated with the task to be executed. Starting execution of the task is performed if the starting address is within the range of addresses. The execution of the task is terminated if an address generated during execution falls outside the range of addresses.

Abstract: A method for writing a set of information for processing by a processing unit of an integrated circuit in an external memory outside the integrated circuit, includes: generating, within the integrated circuit, an encryption key; for each item of information intended to be written at an address of the external memory, first encrypting the address within the integrated circuit by a first encryption/decryption circuit using the encryption key to obtain an encrypted address; second encrypting the item of information within the integrated circuit using a second encryption/decryption circuit using the encrypted address to obtain an encrypted item of information; and writing the encrypted item of information at the address of the external memory, wherein the external memory is not able to be written twice at a same address during a write process

Abstract: Several first digital streams of first digital samples at a first sampling frequency are processed to issue corresponding stream that are converted into second digital streams sampled at a second sampling frequency lower than said first sampling frequency. At least one delay to be applied to at least one first digital stream to satisfy a condition on the second digital streams is determined and applied to at least one first digital stream before converting. The converting operation performed is decimation filtering of the first digital streams. The application of the at least one delay to at least one first steam involves skipping a number of first digital samples in the at least one first digital stream. The number skipped depends on the value of the at least one delay. Samples that are skipped are not delivered for decimation filtering.

Abstract: An apparatus having a microcontroller includes a processing unit, an internal communication bus assembly, a volatile memory, a non-volatile memory, a logic error management circuit, and two interface circuits. A first interface circuit couples the processing unit to the volatile memory via the internal communication bus assembly. A second interface circuit couples the processing unit to the non-volatile memory via the internal communication bus assembly. When the microcontroller is operating, the interface circuits are arranged to retrieve and evaluate requested data from their respective memory without intervention from the processing unit. In the event a failure is detected, the logic error management circuit is arranged to assert a stop signal. In some cases, detecting a failure includes comparing a check value stored in memory with a check value calculated from the data retrieved from memory.

Abstract: An embodiment system includes a first processor configured to process a suite of instructions and a second processor configured to process a subset of the suite of instructions. The system further includes a power management circuit configured to select the first processor or the second processor as a selected processor, the power management circuit being further configured to activate the selected processor or place the selected processor on standby. The system also includes a first peripheral device configured to generate a first interrupt signal, a switch configured to direct the first interrupt signal to the selected processor, and a first memory configured to store a first interrupt routine associated with the first interrupt signal, the selected processor being configured to execute the first interrupt routine in response to the first interrupt signal.

Abstract: An apparatus having a microcontroller includes a processing unit, an internal communication bus assembly, a volatile memory, a non-volatile memory, a logic error management circuit, and two interface circuits. A first interface circuit couples the processing unit to the volatile memory via the internal communication bus assembly. A second interface circuit couples the processing unit to the non-volatile memory via the internal communication bus assembly. When the microcontroller is operating, the interface circuits are arranged to retrieve and evaluate requested data from their respective memory without intervention from the processing unit. In the event a failure is detected, the logic error management circuit is arranged to assert a stop signal. In some cases, detecting a failure includes comparing a check value stored in memory with a check value calculated from the data retrieved from memory.

Abstract: Several first digital streams of first digital samples at a first sampling frequency are processed to issue corresponding stream that are converted into second digital streams sampled at a second sampling frequency lower than said first sampling frequency. At least one delay to be applied to at least one first digital stream to satisfy a condition on the second digital streams is determined and applied to at least one first digital stream before converting. The converting operation performed is decimation filtering of the first digital streams. The application of the at least one delay to at least one first steam involves skipping a number of first digital samples in the at least one first digital stream. The number skipped depends on the value of the at least one delay. Samples that are skipped are not delivered for decimation filtering.

Abstract: Embodiments described in the present disclosure relate to a method of processing faults in a control unit, the method including: upon each request for reading a datum in a first memory, received by a first interface circuit for accessing the first memory, calculating by means of the first interface circuit, a check word based on the datum read, if the check word calculated is different from a check word read in the memory in association with the datum read, activating an error signal by means of the first interface circuit, and sending the error signal to an output circuit of the control unit, without using any circuits of the control unit, likely to send a request to access the first memory.

Abstract: A multifunctional timer/event counter device includes at least one counter controlled by a clock signal, and a control register including at least one binary number that will at least define a behavior of the counter. The device also includes a function module including at least one synchronization signal reception input and a reception input for at least one function control signal, the function module being capable of modifying the binary number as a function of at least the synchronization signal and the function control signal.

Abstract: The present invention relates to a method for managing the stack of a microprocessor comprising a central processing unit and a memory array, the central processing unit comprising registers containing contextual data and a stack pointer, the stack being a zone of the memory array used for saving contextual data upon a switch from a first to a second program. According to the present invention, the method comprises saving contextual data contained in a variable number of registers that varies according to the value of at least one flag stored in a register to be saved. Advantages: optimization of the filling of the stack and of the number of subprograms that can be interleaved.

Abstract: A multifunctional timer/event counter device includes at least one counter controlled by a clock signal, and a control register including at least one binary number that will at least define a behavior of the counter. The device also includes a function module including at least one synchronization signal reception input and a reception input for at least one function control signal, the function module being capable of modifying the binary number as a function of at least the synchronization signal and the function control signal.

Abstract: A system is provided for controlling access to protected data. The system includes storage means, protection means, an internal key, and means for receiving an input key from the outside. The storage means includes a protected zone for storing the protected data, and a command input for denying or authorising access to the protected data. The protection means controls access to the protected data by selectively activating the command input of the memory. The protection means authorises access to the protected data only when the internal key and the input key are identical. Also provided is a method for controlling access to protected data stored in a protected zone of a storage means. According to the method, an input key is received from the outside, and access to the protected data is authorised only when the input key and an internal are identical.

Abstract: An electronic device for storing protected data is disclosed. The electronic device includes memory protection logic operable to interface with memory, such as non-volatile ROM for storing protected data therein. The protected data in one embodiment is program code. The access to the protected data is restricted by a local processor, such as a microcontroller or microprocessor for execution thereon within the electronic device. Further, the electronic device includes validation logic operative in a first mode, for checking the validity of the data and for producing a validity signal, such as a checksum, enabled to determine whether that data is valid. In order to prevent access to intermediate validity calculations which may allow an individual to gain knowledge of the protected data, a validity signal output control is provided for inhibiting an output of the validity signal to outside the device until the validity of a predetermined quantity of the protected data has been checked.

Abstract: A programmable clock generator delivers, using a primary clock signal of determined frequency, a first clock signal the frequency of which is equal to the frequency of the primary clock signal divided by a set point M. The set point M is a decimal number comprising a whole part M1 and a decimal part M2 and the clock generator modulates the period of the pulses of the first clock signal so that the duration of Ni successive pulses is substantially equal to M*Ni times the period of the primary clock signal, Ni being a reference number for modulating the period of the pulses of the first clock signal.

Abstract: A microcontroller includes a microprocessor (2), a reset circuit (3) selectively generating a signal for resetting the microprocessor (2), and a detection device (4), having at least one input for receiving (5) a vital logic signal from the microcontroller and an output (6) applying a reset command to the reset circuit upon detecting a change in the logic state of the vital logic signal. A computer system can include one or more of the microcontroller.