Abstract: In some embodiments, a system includes a memory testing circuit configured to perform a test to determine whether a portion of a memory is operational at a specified amount of time after a power-up request by performing operations. The operations may include sending a power-up request to the portion. The operations may further include sending, at the specified amount of time after the power-up request, a write request for a write operation at the portion. The operations may further include sending a read request that requests a read operation for data written by the write operation. The operations may further include determining, based on data received in response to the read request, whether the portion correctly performed the read operation and the write operation.

Abstract: Techniques are disclosed relating to memory testing. In one embodiment, an integrated circuit is disclosed that includes a memory and an interface circuit. The interface circuit is configured to receive one or more testing signals from a built in self-test (BIST) unit. The interface circuit is further configured to receive, independently from the one or more testing signals, one or more configuration signals from automated test equipment (ATE). The interface circuit is further configured to issue one or more instruction signals to the memory based on the one or more testing signals and based on the one or more configuration signals. In some embodiments, the interface circuit is configured to enable the BIST unit to detect errors in functions the BIST unit is not designed to test.

Abstract: In some embodiments, a system includes a memory testing circuit configured to perform a test of an internal comparator of a memory circuit by performing operations. The operations may include causing a first value to be stored at the memory circuit as a current data value. The operations may further include subsequently causing the first value to be sent to the memory circuit as a current comparison data value. The operations may further include causing the internal comparator to compare the current data value to the current comparison data value. The operations may further include receiving a current match value that indicates whether the current data value matches the current comparison data value. In some embodiments, the memory testing circuit may be configured to enable a self-test circuit to detect errors regarding functions of the memory circuit that the self-test circuit is not designed to test.

Abstract: Techniques are disclosed relating to memory testing. In one embodiment, an integrated circuit is disclosed that includes a memory and an interface circuit. The interface circuit is configured to receive one or more testing signals from a built in self-test (BIST) unit. The interface circuit is further configured to receive, independently from the one or more testing signals, one or more configuration signals from automated test equipment (ATE). The interface circuit is further configured to issue one or more instruction signals to the memory based on the one or more testing signals and based on the one or more configuration signals. In some embodiments, the interface circuit is configured to enable the BIST unit to detect errors in functions the BIST unit is not designed to test.

Abstract: Techniques are disclosed relating to testing logic in integrated circuits based on power being received by the integrated circuit. In one embodiment, an integrated circuit includes a memory and a self-test unit. The self-test unit is configured to receive an indication that identifies a memory block as being in a low-power state and to determine whether to disregard test data read from the one or more memory banks. In some embodiments, the self-test unit may be configured to mask a portion of test result related to the test data that the self-test unit has determined to disregard. The self-test unit may include an error validation logic configured to determine a validity of test data received from a memory based on a power activation status (e.g., whether the memory is powered on or off) associated with the memory.

Abstract: Techniques are disclosed relating to memory testing. In one embodiment, an integrated circuit is disclosed that includes a memory and an interface circuit. The interface circuit is configured to receive one or more testing signals from a built in self-test (BIST) unit. The interface circuit is further configured to receive, independently from the one or more testing signals, one or more configuration signals from automated test equipment (ATE). The interface circuit is further configured to issue one or more instruction signals to the memory based on the one or more testing signals and based on the one or more configuration signals. In some embodiments, the interface circuit is configured to enable the BIST unit to detect errors in functions the BIST unit is not designed to test.

Abstract: Techniques are disclosed relating to testing logic in integrated circuits based on power being received by the integrated circuit. In one embodiment, an integrated circuit includes a memory and a self-test unit. The self-test unit is configured to receive an indication that identifies a memory block as being in a low-power state and to determine whether to disregard test data read from the one or more memory banks. In some embodiments, the self-test unit may be configured to mask a portion of test result related to the test data that the self-test unit has determined to disregard. The self-test unit may include an error validation logic configured to determine a validity of test data received from a memory based on a power activation status (e.g., whether the memory is powered on or off) associated with the memory.

Abstract: Techniques are disclosed relating to memory testing. In one embodiment, an integrated circuit is disclosed that includes a memory and an interface circuit. The interface circuit is configured to receive one or more testing signals from a built in self-test (BIST) unit. The interface circuit is further configured to receive, independently from the one or more testing signals, one or more configuration signals from automated test equipment (ATE). The interface circuit is further configured to issue one or more instruction signals to the memory based on the one or more testing signals and based on the one or more configuration signals. In some embodiments, the interface circuit is configured to enable the BIST unit to detect errors in functions the BIST unit is not designed to test.