Patents by Inventor Dragos SEGHETE

Dragos SEGHETE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11489112
    Abstract: An apparatus, includes an interconnect, including a conductive material, above a substrate and a resistive random access memory (RRAM) device coupled to the interconnect. The RRAM device includes an electrode structure above the interconnect, where an upper portion of the electrode structure has a first width. The RRAM device further includes a switching layer on the electrode structure, where the switching layer has the first width and an oxygen exchange layer, having a second width less than the first width, on a portion of the switching layer. The RRAM device further includes a top electrode above the oxygen exchange layer, where the top electrode has the second width and an encapsulation layer on a portion of the switching layer, where the switching layer extends along a sidewall of the oxygen exchange layer.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: November 1, 2022
    Assignee: INTEL CORPORATION
    Inventors: Namrata S. Asuri, Oleg Golonzka, Nathan Strutt, Patrick J. Hentges, Trinh T. Van, Hiten Kothari, Ameya S. Chaudhari, Matthew J. Andrus, Timothy E. Glassman, Dragos Seghete, Christopher J. Wiegand, Daniel G. Ouellette
  • Patent number: 11430948
    Abstract: A memory device includes a bottom electrode above a substrate, a first switching layer on the bottom electrode, a second switching layer including aluminum on the first switching layer, an oxygen exchange layer on the second switching layer and a top electrode on the oxygen exchange layer. The presence of the second switching layer including aluminum on the first switching layer enables a reduction in electro-forming voltage of the memory device.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: August 30, 2022
    Assignee: INTEL CORPORATION
    Inventors: Timothy Glassman, Dragos Seghete, Nathan Strutt, Namrata S. Asuri, Oleg Golonzka, Hiten Kothari, Matthew J. Andrus
  • Patent number: 11342499
    Abstract: Approaches for fabricating RRAM stacks with reduced forming voltage, and the resulting structures and devices, are described. In an example, a resistive random access memory (RRAM) device includes a conductive interconnect in an inter-layer dielectric (ILD) layer above a substrate. An RRAM element is on the conductive interconnect, the RRAM element including a first electrode layer on the uppermost surface of the conductive interconnect. A resistance switching layer is on the first electrode layer, the resistance switching layer including a first metal oxide material layer on the first electrode layer, and a second metal oxide material layer on the first metal oxide material layer, the second metal oxide material layer including a metal species not included in the first metal oxide material layer. An oxygen exchange layer is on the second metal oxide material layer of the resistance switching layer. A second electrode layer is on the oxygen exchange layer.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: May 24, 2022
    Assignee: Intel Corporation
    Inventors: Timothy E. Glassman, Dragos Seghete, Nathan Strutt, Namrata S. Asuri, Oleg Golonzka
  • Publication number: 20220102343
    Abstract: Multi-layer etch stop layers are described. In an example, an integrated circuit structure includes a conductive line in a first interlayer dielectric material above a substrate. A first dielectric etch stop layer, a second dielectric layer and a third dielectric layer are on the conductive line and the first interlayer dielectric material. A second interlayer dielectric material is on the third dielectric etch stop layer. An opening is in the second interlayer dielectric material, in the third dielectric etch stop layer, and in the second dielectric etch stop layer, in the first dielectric etch stop layer. A conductive structure is in the opening, the conductive structure in direct contact with the conductive line.
    Type: Application
    Filed: September 25, 2020
    Publication date: March 31, 2022
    Inventors: Anthony V. MULE', David J. TOWNER, Dragos SEGHETE, Christopher R. RYDER, Angel AQUINO GONZALEZ
  • Publication number: 20220068794
    Abstract: Metal insulator metal capacitors are described. In an example, a capacitor includes a first electrode plate, and a first capacitor dielectric on the first electrode plate. A second electrode plate is on the first capacitor dielectric and is over and parallel with the first electrode plate, and a second capacitor dielectric is on the second electrode plate. A third electrode plate is on the second capacitor dielectric and is over and parallel with the second electrode plate, and a third capacitor dielectric is on the third electrode plate. A fourth electrode plate is on the third capacitor dielectric and is over and parallel with the third electrode plate. In another example, a capacitor includes a first electrode, a capacitor dielectric on the first electrode, and a second electrode on the capacitor dielectric. The capacitor dielectric includes a plurality of alternating first dielectric layers and second dielectric layers.
    Type: Application
    Filed: December 21, 2020
    Publication date: March 3, 2022
    Inventors: Aaron J. WELSH, Christopher M. PELTO, David J. TOWNER, Mark A. BLOUNT, Takayoshi ITO, Dragos SEGHETE, Christopher R. RYDER, Stephanie F. SUNDHOLM, Chamara ABEYSEKERA, Anil W. DEY, Che-Yun LIN, Uygar E. AVCI
  • Publication number: 20200203602
    Abstract: An apparatus, includes an interconnect, including a conductive material, above a substrate and a resistive random access memory (RRAM) device coupled to the interconnect. The RRAM device includes an electrode structure above the interconnect, where an upper portion of the electrode structure has a first width. The RRAM device further includes a switching layer on the electrode structure, where the switching layer has the first width and an oxygen exchange layer, having a second width less than the first width, on a portion of the switching layer. The RRAM device further includes a top electrode above the oxygen exchange layer, where the top electrode has the second width and an encapsulation layer on a portion of the switching layer, where the switching layer extends along a sidewall of the oxygen exchange layer.
    Type: Application
    Filed: September 28, 2017
    Publication date: June 25, 2020
    Applicant: INTEL CORPORATION
    Inventors: Namrata S. Asuri, Oleg Golonzka, Nathan Strutt, Patrick J. Hentges, Trinh T. Van, Hiten Kothari, Ameya S. Chaudhari, Matthew J. Andrus, Timothy E. Glassman, Dragos Seghete, Christopher J. Wiegand, Daniel G. Ouellette
  • Publication number: 20200203603
    Abstract: A memory device includes a bottom electrode above a substrate, a first switching layer on the bottom electrode, a second switching layer including aluminum on the first switching layer, an oxygen exchange layer on the second switching layer and a top electrode on the oxygen exchange layer. The presence of the second switching layer including aluminum on the first switching layer enables a reduction in electro-forming voltage of the memory device.
    Type: Application
    Filed: September 28, 2017
    Publication date: June 25, 2020
    Applicant: INTEL CORPORATION
    Inventors: Timothy Glassman, Dragos Seghete, Nathan Strutt, Namrata S. Asuri, Oleg Golonzka, Hiten Kothari, Matthew J. Andrus
  • Publication number: 20200144496
    Abstract: Approaches for fabricating RRAM stacks with reduced forming voltage, and the resulting structures and devices, are described. In an example, a resistive random access memory (RRAM) device includes a conductive interconnect in an inter-layer dielectric (ILD) layer above a substrate. An RRAM element is on the conductive interconnect, the RRAM element including a first electrode layer on the uppermost surface of the conductive interconnect. A resistance switching layer is on the first electrode layer, the resistance switching layer including a first metal oxide material layer on the first electrode layer, and a second metal oxide material layer on the first metal oxide material layer, the second metal oxide material layer including a metal species not included in the first metal oxide material layer. An oxygen exchange layer is on the second metal oxide material layer of the resistance switching layer. A second electrode layer is on the oxygen exchange layer.
    Type: Application
    Filed: September 18, 2017
    Publication date: May 7, 2020
    Inventors: Timothy E. GLASSMAN, Dragos SEGHETE, Nathan STRUTT, Namrata S. ASURI, Oleg GOLONZKA