Patents by Inventor Drew Delaney

Drew Delaney has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Die-stacking using through-silicon vias on bumpless build-up layer substrates including embedded-dice, and processes of forming same
    Patent number: 9406618
    Abstract: An apparatus includes a coreless substrate with a through-silicon via (TSV) embedded die that is integral to the coreless substrate. The apparatus includes a subsequent die that is coupled to the TSV die and that is disposed above the coreless substrate.
    Type: Grant
    Filed: June 16, 2014
    Date of Patent: August 2, 2016
    Assignee: Intel Corporation
    Inventors: John S. Guzek, Ravi K. Nalla, Javier Solo Gonzalez, Drew Delaney, Suresh Pothukuchi, Mohit Mamodia, Edward Zarbock, Johanna M. Swan
  • DIE-STACKING USING THROUGH-SILICON VIAS ON BUMPLESS BUILD-UP LAYER SUBSTRATES INCLUDING EMBEDDED-DICE, AND PROCESSES OF FORMING SAME
    Publication number: 20140327149
    Abstract: An apparatus includes a coreless substrate with a through-silicon via (TSV) embedded die that is integral to the coreless substrate. The apparatus includes a subsequent die that is coupled to the TSV die and that is disposed above the coreless substrate.
    Type: Application
    Filed: July 16, 2014
    Publication date: November 6, 2014
    Inventors: John S. Guzek, Ravi K. Nalla, Javier Solo Gonzalez, Drew Delaney, Suresh Pothukuchi, Mohit Mamodia, Edward Zarbock, Johanna M. Swan
  • DIE-STACKING USING THROUGH-SILICON VIAS ON BUMPLESS BUILD-UP LAYER SUBSTRATES INCLUDING EMBEDDED-DICE, AND PROCESSES OF FORMING SAME
    Publication number: 20140295621
    Abstract: An apparatus includes a coreless substrate with a through-silicon via (TSV) embedded die that is integral to the coreless substrate. The apparatus includes a subsequent die that is coupled to the TSV die and that is disposed above the coreless substrate.
    Type: Application
    Filed: June 16, 2014
    Publication date: October 2, 2014
    Inventors: John S. Guzek, Ravi K. Nalla, Javier Solo Gonzalez, Drew Delaney, Suresh Pothukuchi, Mohit Mamodia, Edward Zarbock, Johanna M. Swan
  • Die-stacking using through-silicon vias on bumpless build-up layer substrates including embedded-dice, and processes of forming same
    Patent number: 8786066
    Abstract: An apparatus includes a coreless substrate with a through-silicon via (TSV) embedded die that is integral to the coreless substrate. The apparatus includes a subsequent die that is coupled to the TSV die and that is disposed above the coreless substrate.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: July 22, 2014
    Assignee: Intel Corporation
    Inventors: John S. Guzek, Ravi K. Nalla, Javier Soto Gonzalez, Drew Delaney, Suresh Pothukuchi, Mohit Mamodia, Edward Zarbock, Johanna M. Swan
  • Forming metal filled die back-side film for electromagnetic interference shielding with coreless packages
    Patent number: 8319318
    Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a carrier material, attaching a die in the cavity, wherein a backside of the die comprises a metal filled DBF, forming a dielectric material adjacent the die and on a bottom side of the carrier material, forming a coreless substrate by building up layers on the dielectric material, and removing the carrier material from the coreless substrate.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: November 27, 2012
    Assignee: Intel Corporation
    Inventors: Ravi K Nalla, Drew Delaney
  • DIE-STACKING USING THROUGH-SILICON VIAS ON BUMPLESS BUILD-UP LAYER SUBSTRATES INCLUDING EMBEDDED-DICE, AND PROCESSES OF FORMING SAME
    Publication number: 20120074581
    Abstract: An apparatus includes a coreless substrate with a through-silicon via (TSV) embedded die that is integral to the coreless substrate. The apparatus includes a subsequent die that is coupled to the TSV die and that is disposed above the coreless substrate.
    Type: Application
    Filed: September 24, 2010
    Publication date: March 29, 2012
    Inventors: John S. Guzek, Ravi K. Nalla, Javier Soto Gonzalez, Drew Delaney, Suresh Pothukuchi, Mohit Mamodia, Edward Zarbock, Johanna M. Swan
  • MICROELECTRONIC PACKAGE AND METHOD OF MANUFACTURING SAME
    Publication number: 20110316140
    Abstract: A microelectronic package includes a substrate (110), a die (120) embedded within the substrate, the die having a front side (121) and a back side (122) and a through-silicon-via (123) therein, build-up layers (130) built up over the front side of the die, and a power plane (140) in physical contact with the back side of the die. In another embodiment, the microelectronic package comprises a substrate (210), a first die (220) and a second die (260) embedded in the substrate and having a front side (221, 261) and a back side (222, 262) and a through-silicon-via (223, 263) therein, build-up layers (230) over the front sides of the first and second dies, and an electrically conductive structure (240) in physical contact with the back sides of the first and second dies.
    Type: Application
    Filed: June 29, 2010
    Publication date: December 29, 2011
    Inventors: Ravi K. Nalla, Mathew J. Manusharow, Drew Delaney
  • FORMING FUNCTIONALIZED CARRIER STRUCTURES WITH CORELESS PACKAGES
    Publication number: 20110254124
    Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material.
    Type: Application
    Filed: April 16, 2010
    Publication date: October 20, 2011
    Inventors: Ravi K. Nalla, John Guzek, Javier Soto Gonzalez, Drew Delaney, Hamid Azimi
  • FORMING METAL FILLED DIE BACK-SIDE FILM FOR ELECTROMAGNETIC INTERFERENCE SHIELDING WITH CORELESS PACKAGES
    Publication number: 20110241186
    Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a carrier material, attaching a die in the cavity, wherein a backside of the die comprises a metal filled DBF, forming a dielectric material adjacent the die and on a bottom side of the carrier material, forming a coreless substrate by building up layers on the dielectric material, and removing the carrier material from the coreless substrate.
    Type: Application
    Filed: April 6, 2010
    Publication date: October 6, 2011
    Inventors: Ravi K. Nalla, Drew Delaney
  • Methods of reducing bleed-out of underfill and adhesive materials
    Publication number: 20050118748
    Abstract: Method of forming microeletronic devices by disposing a radiation curable underfill material or adhesive material between a substrate and a microelectronic die, and exposing any the radiation curable material which bleeds-out therefrom to radiation before or immediately after disposition, thereby reducing the extent of material bleed-out.
    Type: Application
    Filed: December 1, 2003
    Publication date: June 2, 2005
    Inventors: Mahesh Sambasivam, Drew Delaney, Saeed Shojaie