Patents by Inventor Drew Eric Wingard
Drew Eric Wingard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240095195Abstract: This disclosure describes various examples of a system which uses a multi-bank, multi-port shared memory system that may be implemented as part of a system on a chip. The shared memory system may have particular applicability in the context of an artificial reality system, and may be designed to have distributed or varied latency for one or more memory banks and/or one or more components or subsystems within the system on a chip. The described shared memory system may be logically a single entity, but physically may have multiple memory banks, each accessible by any of a number of components or subsystems. In some examples, the memory system may enable concurrent, common, and/or shared access to memory without requiring, in some situations, full locking or arbitration.Type: ApplicationFiled: November 29, 2023Publication date: March 21, 2024Inventors: Alok Kumar MATHUR, Ennio SALEMI, Drew Eric WINGARD, Valerio CATALANO
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Patent number: 11868281Abstract: This disclosure describes various examples of a system which uses a multi-bank, multi-port shared memory system that may be implemented as part of a system on a chip. The shared memory system may have particular applicability in the context of an artificial reality system, and may be designed to have distributed or varied latency for one or more memory banks and/or one or more components or subsystems within the system on a chip. The described shared memory system may be logically a single entity, but physically may have multiple memory banks, each accessible by any of a number of components or subsystems. In some examples, the memory system may enable concurrent, common, and/or shared access to memory without requiring, in some situations, full locking or arbitration.Type: GrantFiled: August 8, 2022Date of Patent: January 9, 2024Assignee: Meta Platforms Technologies, LLCInventors: Alok Kumar Mathur, Ennio Salemi, Drew Eric Wingard, Valerio Catalano
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Publication number: 20230267078Abstract: A system and method for accessing cache lines of an N-way set associative cache distributed across local memory of compute elements. The set associative cache includes a plurality of sets, with each location in cacheable local memory mapped to one of the sets and each set including N locations for caching data blocks read from the cacheable memory. Each set is mapped to one of the local memories, when that local memory is not in use by local compute elements. A cache controller is configured to receive a read request, to identify a data block in the cacheable memory associated with the address, to determine if the identified data block is in cache in one of the local memories, and, if the identified data block is in cache in one of the local memories, to fetch the identified data block from the cache.Type: ApplicationFiled: May 2, 2023Publication date: August 24, 2023Inventors: Sridhar Gurumurthy Isukapalli Sharma, Drew Eric Wingard
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Patent number: 11681627Abstract: A system and method for accessing cache lines of an N-way set associative cache distributed across local memory of compute elements. The set associative cache includes a plurality of sets, with each location in cacheable local memory mapped to one of the sets and each set including N locations for caching data blocks read from the cacheable memory. Each set is mapped to one of the local memories, when that local memory is not in use by local compute elements. A cache controller is configured to receive a read request, to identify a data block in the cacheable memory associated with the address, to determine if the identified data block is in cache in one of the local memories, and, if the identified data block is in cache in one of the local memories, to fetch the identified data block from the cache.Type: GrantFiled: October 18, 2021Date of Patent: June 20, 2023Assignee: Meta Platforms Technologies, LLCInventors: Sridhar Gurumurthy Isukapalli Sharma, Drew Eric Wingard
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Publication number: 20220391331Abstract: This disclosure describes various examples of a system which uses a multi-bank, multi-port shared memory system that may be implemented as part of a system on a chip. The shared memory system may have particular applicability in the context of an artificial reality system, and may be designed to have distributed or varied latency for one or more memory banks and/or one or more components or subsystems within the system on a chip. The described shared memory system may be logically a single entity, but physically may have multiple memory banks, each accessible by any of a number of components or subsystems. In some examples, the memory system may enable concurrent, common, and/or shared access to memory without requiring, in some situations, full locking or arbitration.Type: ApplicationFiled: August 8, 2022Publication date: December 8, 2022Inventors: Alok Kumar Mathur, Ennio Salemi, Drew Eric Wingard, Valerio Catalano
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Patent number: 11474970Abstract: The disclosure describes techniques for interrupt and inter-processor communication (IPC) mechanisms that are shared among computer processors. For example, an artificial reality system includes a plurality of processors; an inter-processor communication (IPC) unit comprising a register, wherein the IPC unit is configured to: receive a memory access request from a first processor of the processors, wherein the memory access request includes information indicative of a hardware identifier (HWID) associated with the first processor; determine whether the HWID associated with the first processor matches an HWID for the register of the IPC unit; and permit, based on determining that the HWID associated with the first processor matches the HWID for the register of the IPC unit, the memory access request to indicate a communication from the first processor to at least one other processor.Type: GrantFiled: December 24, 2019Date of Patent: October 18, 2022Assignee: Meta Platforms Technologies, LLCInventors: Jun Wang, Neeraj Upasani, Wojciech Stefan Powiertowski, Drew Eric Wingard, Gregory Edward Ehmann, Marco Brambilla, Minli Lin, Miguel Angel Guerrero
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Patent number: 11409671Abstract: This disclosure describes various examples of a system which uses a multi-bank, multi-port shared memory system that may be implemented as part of a system on a chip. The shared memory system may have particular applicability in the context of an artificial reality system, and may be designed to have distributed or varied latency for one or more memory banks and/or one or more components or subsystems within the system on a chip. The described shared memory system may be logically a single entity, but physically may have multiple memory banks, each accessible by any of a number of components or subsystems. In some examples, the memory system may enable concurrent, common, and/or shared access to memory without requiring, in some situations, full locking or arbitration.Type: GrantFiled: December 19, 2019Date of Patent: August 9, 2022Assignee: Facebook Technologies, LLCInventors: Alok Kumar Mathur, Ennio Salemi, Drew Eric Wingard, Valerio Catalano
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Publication number: 20210089366Abstract: The disclosure describes techniques for interrupt and inter-processor communication (IPC) mechanisms that are shared among computer processors. For example, an artificial reality system includes a plurality of processors; an inter-processor communication (IPC) unit comprising a register, wherein the IPC unit is configured to: receive a memory access request from a first processor of the processors, wherein the memory access request includes information indicative of a hardware identifier (HWID) associated with the first processor; determine whether the HWID associated with the first processor matches an HWID for the register of the IPC unit; and permit, based on determining that the HWID associated with the first processor matches the HWID for the register of the IPC unit, the memory access request to indicate a communication from the first processor to at least one other processor.Type: ApplicationFiled: December 24, 2019Publication date: March 25, 2021Inventors: Jun Wang, Neeraj Upasani, Wojciech Stefan Powiertowski, Drew Eric Wingard, Gregory Edward Ehmann, Marco Brambilla, Minli Lin, Miguel Angel Guerrero
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Publication number: 20210089475Abstract: This disclosure describes various examples of a system which uses a multi-bank, multi-port shared memory system that may be implemented as part of a system on a chip. The shared memory system may have particular applicability in the context of an artificial reality system, and may be designed to have distributed or varied latency for one or more memory banks and/or one or more components or subsystems within the system on a chip. The described shared memory system may be logically a single entity, but physically may have multiple memory banks, each accessible by any of a number of components or subsystems. In some examples, the memory system may enable concurrent, common, and/or shared access to memory without requiring, in some situations, full locking or arbitration.Type: ApplicationFiled: December 19, 2019Publication date: March 25, 2021Inventors: Alok Kumar Mathur, Ennio Salemi, Drew Eric Wingard, Valerio Catalano
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Patent number: 7356633Abstract: Embodiments of apparatuses, systems, and methods are described for composing on-chip interconnects with configurable interfaces. A configurable interface includes a configurable agent and interface port. The configurable agent has a first input and a first output with the first input receiving a first communication. An input of a core receives the configurable agent's first output. The agent is configured for important inter-network characteristics such as topology, flooding control, clocking/reset, and performance enhancement.Type: GrantFiled: May 3, 2002Date of Patent: April 8, 2008Assignee: Sonics, Inc.Inventors: Wolf-Dietrich Weber, Chien-Chun Chou, Nabil N. Masri, Michael Jude Meyer, Thomas Wayne O'Connell, Kamil Synek, Jay Scott Tomlinson, Drew Eric Wingard
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Patent number: 7325221Abstract: A core block with a highly configurable interface such that the interface of the core can be optimally configured for the system the core is integrated into. In one embodiment the method consists of defining a configurable interface with different configuration options, capturing the specific core configuration through manual entry or through the use of a Graphical User Interface, and providing for software that combines the source description of the core with the configuration data to generate the core with an optimally configured logic and circuit interface.Type: GrantFiled: August 8, 2000Date of Patent: January 29, 2008Assignee: Sonics, IncorporatedInventors: Drew Eric Wingard, Michael J. Meyer, Geert P. Rosseel, Lisa Robinson, Jay Tomlinson
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Patent number: 7302691Abstract: Embodiments of methods and apparatuses for multicast handling in mixed core systems have been described. A method for multicast handling in mixed core systems includes configuring broadcast group registers located in targets. The method also includes receiving a request to create a broadcast group and creating the broadcast group. Finally, the method includes transmitting the broadcast group to targets with broadcast group registers that correspond to the broadcast group.Type: GrantFiled: May 10, 2002Date of Patent: November 27, 2007Assignee: Sonics, IncorporatedInventors: Nabil N. Masri, Wolf-Dietrich Weber, Chien-Chun Chou, Drew Eric Wingard
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Patent number: 7266786Abstract: A method and apparatus of a configurable address mapping and protection architecture and hardware for on-chip systems have been described.Type: GrantFiled: November 5, 2002Date of Patent: September 4, 2007Assignee: Sonics, Inc.Inventors: Chien-Chun Chou, Jay Scott Tomlinson, Wolf-Dietrich Weber, Drew Eric Wingard, Sricharan Kasetti
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Patent number: 7254603Abstract: A method and apparatus for on-chip inter-network performance optimization using configurable performance parameters have been described.Type: GrantFiled: May 3, 2002Date of Patent: August 7, 2007Assignee: Sonics, Inc.Inventors: Wolf-Dietrich Weber, Chien-Chun Chou, Nabil N. Masri, Michael Jude Meyer, Thomas Wayne O'Connell, Kamil Synek, Jay Scott Tomlinson, Drew Eric Wingard
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Patent number: 7194566Abstract: A communication system and method with configurable posting points have been described.Type: GrantFiled: May 3, 2002Date of Patent: March 20, 2007Assignee: Sonics, Inc.Inventors: Drew Eric Wingard, Chien-Chun Chou, Nabil N. Masri, Thomas Wayne O'Connell, Jay Scott Tomlinson, Wolf-Dietrich Weber
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Patent number: 7120712Abstract: A communication system. One embodiment includes at least two functional blocks, wherein an first functional block communicates with a second functional block by establishing a connection, wherein a connection is a logical state in which data may pass between the first functional block and the second functional block. One embodiment includes a bus coupled to each of the functional blocks and configured to carry a plurality of signals. The plurality of signals includes a connection identifier that indicates a particular connection that a data transfer is part of, and a thread identifier that indicates a transaction stream that the data transfer is part of.Type: GrantFiled: February 25, 2004Date of Patent: October 10, 2006Assignee: Sonics, Inc.Inventors: Drew Eric Wingard, Geert-Paul Rosseel, Jay S. Tomlinson, Lisa A. Robinson
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Publication number: 20040177186Abstract: A communication system. One embodiment includes at least two functional blocks, wherein an first functional block communicates with a second functional block by establishing a connection, wherein a connection is a logical state in which data may pass between the first functional block and the second functional block. One embodiment includes a bus coupled to each of the functional blocks and configured to carry a plurality of signals. The plurality of signals includes a connection identifier that indicates a particular connection that a data transfer is part of, and a thread identifier that indicates a transaction stream that the data transfer is part of.Type: ApplicationFiled: February 25, 2004Publication date: September 9, 2004Inventors: Drew Eric Wingard, Geert-Paul Rosseel, Jay S. Tomlinson, Lisa A. Robinson
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Publication number: 20040088566Abstract: A method and apparatus of a configurable address mapping and protection architecture and hardware for on-chip systems have been described.Type: ApplicationFiled: November 5, 2002Publication date: May 6, 2004Applicant: Sonics, Inc.Inventors: Chien-Chun Chou, Jay Scott Tomlinson, Wolf-Dietrich Weber, Drew Eric Wingard, Sricharan Kasetti
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Patent number: 6725313Abstract: A communication system. One embodiment includes at least two functional blocks, wherein an first functional block communicates with a second functional block by establishing a connection, wherein a connection is a logical state in which data may pass between the first functional block and the second functional block. One embodiment includes a bus coupled to each of the functional blocks and configured to carry a plurality of signals. The plurality of signals includes a connection identifier that indicates a particular connection that a data transfer is part of, and a thread identifier that indicates a transaction stream that the data transfer is part of.Type: GrantFiled: November 21, 2000Date of Patent: April 20, 2004Assignee: Sonics, Inc.Inventors: Drew Eric Wingard, Geert Paul Rosseel, Jay S. Tomlinson, Lisa A. Robinson
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Publication number: 20030212743Abstract: A method and apparatus for multicast handling in mixed core systems have been described.Type: ApplicationFiled: May 10, 2002Publication date: November 13, 2003Applicant: Sonics, Inc.Inventors: Nabil N. Masri, Wolf-Dietrich Weber, Chien-Chun Chou, Drew Eric Wingard