Patents by Inventor Drew Fairbanks

Drew Fairbanks has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • INTEGRATED CIRCUIT HAVING VERTICAL ROUTING TO BOND PADS
    Publication number: 20240055466
    Abstract: Methods and apparatus for an assembly having directly bonded first and second wafers where the assembly includes a backside surface and a front side surface. The first wafer includes IO signal connections vertically routed to the direct bonding interface by a first one of the bonding posts on the first wafer bonded to a first one of the bonding posts on the second wafer. The second wafer includes vertical routing of the IO signal connections from first one though the bonding posts on the second wafer to IO pads on a backside surface of the assembly.
    Type: Application
    Filed: October 25, 2023
    Publication date: February 15, 2024
    Applicant: Raytheon Company
    Inventors: Eric Miller, Christian M. Boemler, Justin Gordon Adams Wehner, Drew Fairbanks, Sean P. Kilcoyne
  • Integrated circuit having vertical routing to bond pads
    Patent number: 11837623
    Abstract: Methods and apparatus for an assembly having directly bonded first and second wafers where the assembly includes a backside surface and a front side surface. The first wafer includes IO signal connections vertically routed to the direct bonding interface by a first one of the bonding posts on the first wafer bonded to a first one of the bonding posts on the second wafer. The second wafer includes vertical routing of the IO signal connections from first one though the bonding posts on the second wafer to IO pads on a backside surface of the assembly.
    Type: Grant
    Filed: October 12, 2020
    Date of Patent: December 5, 2023
    Assignee: Raytheon Company
    Inventors: Eric Miller, Christian M. Boemler, Justin Gordon Adams Wehner, Drew Fairbanks, Sean P. Kilcoyne
  • INTEGRATED CIRCUIT HAVING VERTICAL ROUTING TO BOND PADS
    Publication number: 20220115423
    Abstract: Methods and apparatus for an assembly having directly bonded first and second wafers where the assembly includes a backside surface and a front side surface. The first wafer includes IO signal connections vertically routed to the direct bonding interface by a first one of the bonding posts on the first wafer bonded to a first one of the bonding posts on the second wafer. The second wafer includes vertical routing of the IO signal connections from first one though the bonding posts on the second wafer to IO pads on a backside surface of the assembly.
    Type: Application
    Filed: October 12, 2020
    Publication date: April 14, 2022
    Applicant: Raytheon Company
    Inventors: Eric Miller, Christian M. Boemler, Justin Gordon Adams Wehner, Drew Fairbanks, Sean P. Kilcoyne