Abstract: A dockable computer system is capable of performing symmetrical multi-processing operations. More particularly, the dockable computer system includes a portable computer and a host station (docking station), each including a resident CPU. The dockable computer system is capable of operating in a docked state in which the portable computer is physically joined with the host station and an undocked state in which the portable computer is physically separate from the host station. In the docked state, the dockable computer system is capable of performing demanding computational tasks such as video conferencing as one of the CPUs in either the portable computer or host station is dedicated to the video conferencing operation. The dockable computer system preferably includes a communication channel for transmitting multi-processing support signals between the portable computer and the host station.

Abstract: A data communication system includes an express bus, a plurality of local buses, and a plurality of local/express bridges, each local/express bridge connecting a corresponding local bus to the express bus. A plurality of local/local bridges each connect two corresponding local buses. The plurality of local buses and the plurality of local/local bridges comprise a local path.

Abstract: Methods and apparatus are disclosed for transferring data to and from the Local Bus of a reduced instruction set computer (RISC) system, to which a first set of high performance devices, including at least one central processor ("CPU"), is attached, and a Remote Bus, to which a second set of relatively lower performance devices is attached, in a manner that does not limit the RISC processor's performance. According to the preferred embodiment of the invention, a RISC architecture is disclosed that includes a novel data transfer controller ("DTC"), or set of DTCs, suitable for performing the aforesaid data transfer function between the high performance Local Bus and one or more Remote Buses to which complete subsystems or peripherals, typically having different (and lower) performance characteristics, are attached. The resulting RISC arthitecture permits commercially available peripherals and subsystems to be used with high performance RISC processors without limiting RISC system performance.

Abstract: Methods and apparatus are disclosed for transferring data to and from a first bus, to which a first set of high performance devices, including at least one central processing unit ("CPU") is attached, and a second bus, to which a second set of relatively lower performance devices is attached. More particularly the invention accomplishes the above transfer function in a manner that facilitates communication between the first and second set of devices from the compartively lower performance of the second set of devices. According to the preferred embodiment of the invention, a data transfer controller i.e., ("DTC") is disclosed that includes a set of direct memory access ("DMA") channels and an input/output controller comprising a set of address mapped I/O ports.

Abstract: Methods and apparatus are disclosed for transferring data to and from a first bus, to which a first set of high performance devices, including at least one central processing unit ("CPU") is attached, and a second bus, to which a second set of relatively lower performance devices is attached. More particularly the invention accomplishes the transfer function in a manner that facilitates communication between the first and second set of devices from the comparatively lower performance of the second set of devices. Direct memory access ("DMA") apparatus and methods are disclosed, including a set of direct memory access channels. The DMA channels may be used to transfer data between the high performance channel (hereinafter referred to as the "Local Bus") coupled to the CPU in a reduced instruction set computer (RISC) system and a typically lower performance, peripheral bus (hereinafter referred to as a "Remote Bus").