Patents by Inventor Drew W. Delaney
Drew W. Delaney has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10375832Abstract: An apparatus including a die including a device side with contact points and lateral sidewalls defining a thickness of the die; a build-up carrier coupled to the die, the build-up carrier including a plurality of alternating layers of patterned conductive material and insulating material, wherein at least one of the layers of patterned conductive material is coupled to one of the contact points of the die; and an interference shield including a conductive material disposed on the die and a portion of the build-up carrier. The apparatus may be connected to a printed circuit board. A method including forming a build-up carrier adjacent a device side of a die including a plurality of alternating layers of patterned conductive material and insulating material; and forming a interference shield on a portion of the build-up carrier.Type: GrantFiled: December 1, 2015Date of Patent: August 6, 2019Assignee: Intel CorporationInventors: Digvijay A. Raorane, Kemal Aygun, Daniel N. Sobieski, Drew W. Delaney
-
Patent number: 9627227Abstract: The present disclosure relates to the field of fabricating microelectronic packages and the fabrication thereof, wherein a microelectronic device may be formed within a bumpless build-up layer coreless (BBUL-C) microelectronic package and wherein a warpage control structure may be disposed on a back surface of the microelectronic device. The warpage control structure may be a layered structure comprising at least one layer of high coefficient of thermal expansion material, including but not limited to a filled epoxy material, and at least one high elastic modulus material layer, such as a metal layer.Type: GrantFiled: August 21, 2014Date of Patent: April 18, 2017Assignee: Intel CorporationInventors: Pramod Malatkar, Drew W. Delaney
-
Publication number: 20160088738Abstract: An apparatus including a die including a device side with contact points and lateral sidewalls defining a thickness of the die; a build-up carrier coupled to the die, the build-up carrier including a plurality of alternating layers of patterned conductive material and insulating material, wherein at least one of the layers of patterned conductive material is coupled to one of the contact points of the die; and an interference shield including a conductive material disposed on the die and a portion of the build-up carrier. The apparatus may be connected to a printed circuit board. A method including forming a build-up carrier adjacent a device side of a die including a plurality of alternating layers of patterned conductive material and insulating material; and forming a interference shield on a portion of the build-up carrier.Type: ApplicationFiled: December 1, 2015Publication date: March 24, 2016Inventors: Digvijay A. RAORANE, Kemal AYGUN, Daniel N. SOBIESKI, Drew W. DELANEY
-
Patent number: 9257380Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material.Type: GrantFiled: February 18, 2015Date of Patent: February 9, 2016Assignee: Intel CorporationInventors: Ravi K. Nalla, John S. Guzek, Javier Soto Gonzalez, Drew W. Delaney, Hamid R. Azimi
-
Patent number: 9232686Abstract: An apparatus including a die including a device side with contact points and lateral sidewalls defining a thickness of the die; a build-up carrier coupled to the die, the build-up carrier including a plurality of alternating layers of patterned conductive material and insulating material, wherein at least one of the layers of patterned conductive material is coupled to one of the contact points of the die; and an interference shield including a conductive material disposed on the die and a portion of the build-up carrier. The apparatus may be connected to a printed circuit board. A method including forming a build-up carrier adjacent a device side of a die including a plurality of alternating layers of patterned conductive material and insulating material; and forming a interference shield on a portion of the build-up carrier.Type: GrantFiled: March 27, 2014Date of Patent: January 5, 2016Assignee: Intel CorporationInventors: Digvijay A. Raorane, Kemal Aygun, Daniel N. Sobieski, Drew W. Delaney
-
Publication number: 20150340312Abstract: A microelectronic package comprises a die (110, 210) and a plurality of electrically conductive layers (120, 220) and electrically insulating layers (130, 230), including a first electrically insulating layer (131, 231) closer to the die than any other electrically insulating layer) and second (132, 232) and third electrically insulating layers (233). Each electrically insulating layer has a corresponding glass transition temperature, coefficient of thermal expansion, and modulus of elasticity. The modulus of elasticity of the second electrically insulating layer is greater than that for the first electrically insulating layer, while CTE1 for the second electrically insulating layer is greater than CTE1 for the first. CTE2 for the third electrically insulating layer is less than CTE2 for the first electrically insulating layer. In an embodiment an electrically insulating layer is a glass cloth layer (140) that is an outermost layer of the microelectronic package.Type: ApplicationFiled: August 5, 2015Publication date: November 26, 2015Applicant: INTEL CorporationInventors: Pramod Malatkar, Drew W. Delaney, Rahul N. Manepalli, Dilan Seneviratne
-
Patent number: 9159649Abstract: A microelectronic package comprises a die (110, 210) and a plurality of electrically conductive layers (120, 220) and electrically insulating layers (130, 230), including a first electrically insulating layer (131, 231) closer to the die than any other electrically insulating layer) and second (132, 232) and third electrically insulating layers (233). Each electrically insulating layer has a corresponding glass transition temperature, coefficient of thermal expansion, and modulus of elasticity. The modulus of elasticity of the second electrically insulating layer is greater than that for the first electrically insulating layer, while CTE1 for the second electrically insulating layer is greater than CTE1 for the first. CTE2 for the third electrically insulating layer is less than CTE2 for the first electrically insulating layer. In an embodiment an electrically insulating layer is a glass cloth layer (140) that is an outermost layer of the microelectronic package.Type: GrantFiled: December 20, 2011Date of Patent: October 13, 2015Assignee: Intel CorporationInventors: Pramod Malatkar, Drew W. Delaney, Rahul N. Manepalli, Dilan Seneviratne
-
Publication number: 20150282395Abstract: An apparatus including a die including a device side with contact points and lateral sidewalls defining a thickness of the die; a build-up carrier coupled to the die, the build-up carrier including a plurality of alternating layers of patterned conductive material and insulating material, wherein at least one of the layers of patterned conductive material is coupled to one of the contact points of the die; and an interference shield including a conductive material disposed on the die and a portion of the build-up carrier. The apparatus may be connected to a printed circuit board. A method including forming a build-up carrier adjacent a device side of a die including a plurality of alternating layers of patterned conductive material and insulating material; and forming a interference shield on a portion of the build-up carrier.Type: ApplicationFiled: March 27, 2014Publication date: October 1, 2015Inventors: Digvijay A. RAORANE, Kemal AYGUN, Daniel N. SOBIESKI, Drew W. DELANEY
-
Publication number: 20150179559Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material.Type: ApplicationFiled: February 18, 2015Publication date: June 25, 2015Applicant: Intel CorporationInventors: Ravi K. Nalla, John S. Guzek, Javier Soto Gonzalez, Drew W. Delaney, Hamid R. Azimi
-
Patent number: 8987065Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material.Type: GrantFiled: November 26, 2013Date of Patent: March 24, 2015Assignee: Intel CorporationInventors: Ravi K. Nailla, John S. Guzek, Javier Soto Gonzalez, Drew W. Delaney, Hamid R. Azimi
-
Publication number: 20140363929Abstract: The present disclosure relates to the field of fabricating microelectronic packages and the fabrication thereof, wherein a microelectronic device may be formed within a bumpless build-up layer coreless (BBUL-C) microelectronic package and wherein a warpage control structure may be disposed on a back surface of the microelectronic device. The warpage control structure may be a layered structure comprising at least one layer of high coefficient of thermal expansion material, including but not limited to a filled epoxy material, and at least one high elastic modulus material layer, such as a metal layer.Type: ApplicationFiled: August 21, 2014Publication date: December 11, 2014Inventors: Pramod Malatkar, Drew W. Delaney
-
Patent number: 8896116Abstract: A microelectronic package includes a substrate (110), a die (120) embedded within the substrate, the die having a front side (121) and a back side (122) and a through-silicon-via (123) therein, build-up layers (130) built up over the front side of the die, and a power plane (140) in physical contact with the back side of the die. In another embodiment, the microelectronic package comprises a substrate (210), a first die (220) and a second die (260) embedded in the substrate and having a front side (221, 261) and a back side (222, 262) and a through-silicon-via (223, 263) therein, build-up layers (230) over the front sides of the first and second dies, and an electrically conductive structure (240) in physical contact with the back sides of the first and second dies.Type: GrantFiled: January 8, 2013Date of Patent: November 25, 2014Assignee: Intel CorporationInventors: Ravi K. Nalla, Mathew J. Manusharow, Drew W. Delaney
-
Patent number: 8848380Abstract: The present disclosure relates to the field of fabricating microelectronic packages and the fabrication thereof, wherein a microelectronic device may be formed within a bumpless build-up layer coreless (BBUL-C) microelectronic package and wherein a warpage control structure may be disposed on a back surface of the microelectronic device. The warpage control structure may be a layered structure comprising at least one layer of high coefficient of thermal expansion material, including but not limited to a filled epoxy material, and at least one high elastic modulus material layer, such as a metal layer.Type: GrantFiled: June 30, 2011Date of Patent: September 30, 2014Assignee: Intel CorporationInventors: Pramod Malatkar, Drew W. Delaney
-
Publication number: 20140084467Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material.Type: ApplicationFiled: November 26, 2013Publication date: March 27, 2014Inventors: Ravi K. Nalla, John S. Guzek, Javier Soto Gonzalez, Drew W. Delaney, Hamid R. Azimi
-
Patent number: 8618652Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material.Type: GrantFiled: April 16, 2010Date of Patent: December 31, 2013Assignee: Intel CorporationInventors: Ravi K Nalla, John S Guzek, Javier Soto Gonzalez, Drew W Delaney, Hamid R Azimi
-
Publication number: 20130270719Abstract: A microelectronic package comprises a die (110, 210) and a plurality of electrically conductive layers (120, 220) and electrically insulating layers (130, 230), including a first electrically insulating layer (131, 231) closer to the die than any other electrically insulating layer) and second (132, 232) and third electrically insulating layers (233). Each electrically insulating layer has a corresponding glass transition temperature, coefficient of thermal expansion, and modulus of elasticity. The modulus of elasticity of the second electrically insulating layer is greater than that for the first electrically insulating layer, while CTE1 for the second electrically insulating layer is greater than CTE1 for the first. CTE2 for the third electrically insulating layer is less than CTE2 for the first electrically insulating layer. In an embodiment an electrically insulating layer is a glass cloth layer (140) that is an outermost layer of the microelectronic package.Type: ApplicationFiled: December 20, 2011Publication date: October 17, 2013Inventors: Pramod Malatkar, Drew W. Delaney, Rahul N. Manepalli, Dilan Seneviratne
-
Patent number: 8507324Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a carrier material, attaching a die in the cavity, wherein a backside of the die comprises a metal filled DBF, forming a dielectric material adjacent the die and on a bottom side of the carrier material, forming a coreless substrate by building up layers on the dielectric material, and removing the carrier material from the coreless substrate.Type: GrantFiled: October 25, 2012Date of Patent: August 13, 2013Assignee: Intel CorporationInventors: Ravi K Nalla, Drew W Delaney
-
Publication number: 20130119544Abstract: A microelectronic package includes a substrate (110), a die (120) embedded within the substrate, the die having a front side (121) and a back side (122) and a through-silicon-via (123) therein, build-up layers (130) built up over the front side of the die, and a power plane (140) in physical contact with the back side of the die. In another embodiment, the microelectronic package comprises a substrate (210), a first die (220) and a second die (260) embedded in the substrate and having a front side (221, 261) and a back side (222, 262) and a through-silicon-via (223, 263) therein, build-up layers (230) over the front sides of the first and second dies, and an electrically conductive structure (240) in physical contact with the back sides of the first and second dies.Type: ApplicationFiled: January 8, 2013Publication date: May 16, 2013Inventors: Ravi K. Nalla, Mathew J. Manusharow, Drew W. Delaney
-
Publication number: 20130052776Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a carrier material, attaching a die in the cavity, wherein a backside of the die comprises a metal filled DBF, forming a dielectric material adjacent the die and on a bottom side of the carrier material, forming a coreless substrate by building up layers on the dielectric material, and removing the carrier material from the coreless substrate.Type: ApplicationFiled: October 25, 2012Publication date: February 28, 2013Inventors: Ravi K. Nalla, Drew W. Delaney
-
Publication number: 20130003319Abstract: The present disclosure relates to the field of fabricating microelectronic packages and the fabrication thereof, wherein a microelectronic device may be formed within a bumpless build-up layer coreless (BBUL-C) microelectronic package and wherein a warpage control structure may be disposed on a back surface of the microelectronic device. The warpage control structure may be a layered structure comprising at least one layer of high coefficient of thermal expansion material, including but not limited to a filled epoxy material, and at least one high elastic modulus material layer, such as a metal layer.Type: ApplicationFiled: June 30, 2011Publication date: January 3, 2013Inventors: PRAMOD MALATKAR, DREW W. DELANEY