Abstract: A microprocessor partially decodes instructions retrieved from main memory before placing them into the microprocessor's integrated instruction cache. Each storage location in the instruction cache includes two slots for decoded instructions. One slot controls one of the microprocessor's integer pipelines and a port to the microprocessor's data cache. A second slot controls the second integer pipeline or one of the microprocessor's floating point units. The instructions retrieved from main memory are decoded by a loader unit which decodes the instructions from the compact form as stored in main memory and places them into the two slots of the instruction cache entry according to their functions. In addition, auxiliary information is placed in the cache entry along with the instruction to control parallel execution as well as emulation of complex instructions.

Abstract: A method and apparatus for executing floating-point instruction pairs in a pipelined manner in which exceptions are predicted during an execution stage. In response to a possible exception, the execution pipeline can stall the pipeline. The floating-point pipeline and the integer pipelines are stalled in an execution stage and a decoding stage, respectively. Once stalled, the floating-point microinstructions are executed, the state of the machine is updated and then any exceptions are reported.

Abstract: A microprocessor partially decodes instructions retrieved from main memory before placing them into the microprocessor's integrated instruction cache. Each storage location in the instruction cache includes two slots for decoded instructions. One slot controls one of the microprocessor's integer pipelines and a port to the microprocessor's data cache. A second slot controls the second integer pipeline or one of the microprocessor's floating point units. The instructions retrieved from main memory are decoded by a loader unit which decodes the instructions from the compact form as stored in main memory and places them into the two slots of the instruction cache entry according to their functions. In addition, auxiliary information is placed in the cache entry along with the instruction to control parallel execution as well as emulation of complex instructions.

Abstract: A method and apparatus for performing SRT division, in which Gray coded quotient bit signals are generated during each iteration from a divisor signal having Gray coded bits, and a dividend signal. Preferably, only the two most significant bits of the divisor signal are encoded into Gray code at the start of the division process, and the Gray coded quotient bit signals are decoded after each iteration, or after the final iteration, for use in generating the final quotient. In a preferred embodiment, the invention is a circuit capable of performing both single-precision and double-precision operations, and includes a pair of alternately operating divider block circuits each for generating a pair of quotient bits during each iteration cycle.