Abstract: A multi-image sensor system includes data, clock, and control buses, an application processor connected to the data bus and the clock bus, and image sensors connected in a daisy chain using the control bus. A first one of the image sensors configured as a master outputs image data to the data bus, outputs a first clock signal to the clock bus, and sends a control signal to a second one of the image sensors in the daisy chain through the control bus. The control signal has a first logic state when output of the first image data starts and a second other logic state when output of the first image data ends. The second image sensor connects itself to the data bus and the master disconnects itself from the data bus according to a state of the first control signal.

Abstract: Methods and systems for shared control of a phase locked loop (PLL) for a multi-port physical layer (PHY) are disclosed. In one aspect, an arbitration logic circuit is coupled to ports of a multi-port PHY sharing a phase locked loop (PLL). Upon receiving an indication that the shared PLL is to be reset, the arbitration logic circuit commands the ports sharing the PLL to enter a state in which any reset of the shared PLL would have minimal or no effect in their operations. In this manner, an integrated circuit (IC) including a multi-port PHY may be configured with only one PLL and associated clock generating logic to provide a clock signal for some or all of its ports, thus reducing its semiconductor area and power consumption. Furthermore, the ports of the multi-port PHY may operate independently from each other obviating any configuration and/or interoperability problems associated with having a shared PLL.

Abstract: Methods and systems for shared control of a phase locked loop (PLL) for a multi-port physical layer (PHY) are disclosed. In one aspect, an arbitration logic circuit is coupled to ports of a multi-port PHY sharing a phase locked loop (PLL). Upon receiving an indication that the shared PLL is to be reset, the arbitration logic circuit commands the ports sharing the PLL to enter a state in which any reset of the shared PLL would have minimal or no effect in their operations. In this manner, an integrated circuit (IC) including a multi-port PHY may be configured with only one PLL and associated clock generating logic to provide a clock signal for some or all of its ports, thus reducing its semiconductor area and power consumption. Furthermore, the ports of the multi-port PHY may operate independently from each other obviating any configuration and/or interoperability problems associated with having a shared PLL.

Abstract: Systems, methods, and computer program products for controlling a plurality of pipelined stages are described. In some implementations, an apparatus is described that includes a pipelined data path including a plurality of adjacent stages, where a stage includes a data store, a valid indicator, and a transfer controller including a state machine having a plurality of states. In some implementations, the stage is configured to send a status indicator different from the valid indicator to the state machine to indicate whether new data is available for processing by the stage in a next cycle, and whether a new data transfer is desired in the next cycle between the stage and the adjacent stage.

Abstract: An integrated circuit resides on a circuit board. During operation, the digital controller integrated circuit produces control signals to control a power supply for delivery of power to a load. The integrated circuit can include multiple connectivity ports, on-board memory, and mode control logic. The multiple connectivity ports such as pins, pads, etc., of the integrated circuit can be configured to provide connections between internal circuitry residing in the integrated circuit and external circuitry residing on a circuit board to which the integrated circuit is attached. The mode control logic monitors a status of one or more connectivity ports of the integrated circuit to detect when a board handler places the digital controller in a power island mode in which the integrated circuit is powered so that the board handler can access (e.g., read/write) the memory in the digital controller integrated circuit while other portions of the board are unpowered.

Abstract: A data partitioning circuit partitions received data and an appended error checking code into a plurality of data lines having a fixed length and a last line. A vector selector inserts a pad vector after the appended error checking code when the last line is less than the first length and not equal to the first fixed length minus a length of the appended error checking code, and selects one of a plurality of error checking vectors, the pad vector having a length providing the last line with the first fixed length when appended thereafter, and the plurality of error checking vectors comprising an initial vector and an error checking code feedback vector. An error checking code calculation circuit performs error checking calculations on the plurality of data lines and the last line to generate an error checking result.

Abstract: An integrated circuit resides on a circuit board. During operation, the digital controller integrated circuit produces control signals to control a power supply for delivery of power to a load. The integrated circuit can include multiple connectivity ports, on-board memory, and mode control logic. The multiple connectivity ports such as pins, pads, etc., of the integrated circuit can be configured to provide connections between internal circuitry residing in the integrated circuit and external circuitry residing on a circuit board to which the integrated circuit is attached. The mode control logic monitors a status of one or more connectivity ports of the integrated circuit to detect when a board handler places the digital controller in a power island mode in which the integrated circuit is powered so that the board handler can access (e.g., read/write) the memory in the digital controller integrated circuit while other portions of the board are unpowered.

Abstract: Methods, circuits, architectures, software and systems for error detection in transmitted data. The method generally includes receiving data and non-data, the data including fixed length data portions, removing non-data; and if the data includes a remainder, adding a zero-pad vector to generate a zero-padded data portion, then checking the data and zero-padded data portions for a transmission error. The circuit generally includes a circuit to detect non-data; a circuit configured to replace non-data with a zero-pad vector; and a circuit to detect a transmission error in data and zero-padded data portions of information, and combine the zero-pad vector with a remaining data portion to form the zero-padded data portion. The present invention enables a single error detection circuit to detect errors, thereby reducing chip area, increasing efficiency, and reducing power consumption.

Abstract: Methods, circuits, architectures, and systems for error detection in transmitted data. The method generally includes the steps of (a) performing an error checking calculation on the transmitted data and appended error checking code; (b) determining the calculated error checking code state; and (c) if it has a predetermined state, indicating that there is no error in the transmitted data. The circuitry generally comprises (1) an error checking code calculation circuit configured to calculate error checking code on the transmitted data and the appended error checking code; (2) a vector selector configured to select one of a plurality of error checking vectors; and (3) a logic circuit configured to determine the calculated error checking code state and, if it has a predetermined state, indicate that there is no error in the transmitted data. The software generally includes a set of instructions configured to implement or carry out the present method.

Abstract: Methods, circuits, architectures, and systems for error detection in transmitted data. The method generally includes the steps of (i) partitioning the unit of digital data into one or more full data lines and a remainder, wherein each of the full data lines comprises a predetermined number of data blocks, each of the data blocks has a first fixed length, the predetermined number is an integer of at least 2, and the remainder has a length less than the predetermined number times the first fixed length; (ii) if the remainder contains at least one data bit, adding to the remainder a padding vector having a length sufficient to generate a padded data line having the predetermined number of data blocks; and (iii) performing error checking calculations on the full data lines and the padded data line. The present invention reduces the chip area and power consumption, while improving system performance.

Abstract: Methods, circuits, architectures, software and systems for error detection in transmitted data. The method generally includes receiving data and non-data, the data including fixed length data portions, removing non-data; and if the data includes a remainder, adding a zero-pad vector to generate a zero-padded data portion, then checking the data and zero-padded data portions for a transmission error. The circuit generally includes a circuit to detect non-data; a circuit configured to replace non-data with a zero-pad vector; and a circuit to detect a transmission error in data and zero-padded data portions of information, and combine the zero-pad vector with a remaining data portion to form the zero-padded data portion. The present invention enables a single error detection circuit to detect errors, thereby reducing chip area, increasing efficiency, and reducing power consumption.