Abstract: A memory device includes content banks configured to store content data and parity banks configured to store parity data for reconstructing the content data. In response to receiving, in a first clock cycle, a first request requesting a first operation to be performed in a first content bank and a second request requesting to write new content data to the first content bank, the memory device performs the first operation in the first content bank, and writes the new content data to a second content bank. The second content bank is selected from a subset of content banks defined by content banks that correspond with parity banks different from parity banks that correspond with the first content bank. The memory device updates, based on the new content data written to the second content bank, parity data in the parity banks that correspond with the second content bank.

Abstract: A method for data storage includes, in a network element, receiving from packet-processing circuitry at least a read command and a write command, for execution in a memory array that includes multiple single-port memory banks. When the read command and the write command are to access different memory banks in the memory array, the read command and the write command are executed for the packet-processing circuitry in the different memory banks in a same memory-access cycle. When the read command and the write command are both to access a first memory bank, a second memory bank of the memory array is selected. The read command is executed in the first memory bank and the write command is executed in the second memory bank, in the same memory-access cycle.

Abstract: A memory supports a write or multiple read operations in any given clock cycle. In a first clock cycle, new content data is written to a particular content memory bank among a set of content memory banks. Also in the first clock cycle, current content data is read from corresponding locations in one or more other content memory banks among the set of content memory banks. New parity data is generated based on the new content data written to the particular content memory bank and the current content data read from the one or more other content memory banks. The new parity data is written to a cache memory associated with the one or more parity banks. In a second clock cycle subsequent to the first clock cycle, the new parity data is transferred from the cache memory to one of the one or more parity memory banks.

Abstract: A first memory device stores (i) a head part of a FIFO queue structured as a linked list (LL) of LL elements arranged in an order in which the LL elements were added to the FIFO queue and (ii) a tail part of the FIFO queue. A second memory device stores a middle part of the FIFO queue, the middle part comprising a LL elements following, in an order, the head part and preceding, in the order, the tail part. A queue controller retrieves LL elements in the head part from the first memory device, moves LL elements in the middle part from the second memory device to the head part in the first memory device prior to the head part becoming empty, and updates LL parameters corresponding to the moved LL elements to indicate storage of the moved LL elements changing from the second memory device to the first memory device.

Abstract: A first memory device stores (i) a head part of a FIFO queue structured as a linked list (LL) of LL elements arranged in an order in which the LL elements were added to the FIFO queue and (ii) a tail part of the FIFO queue. A second memory device stores a middle part of the FIFO queue, the middle part comprising a LL elements following, in an order, the head part and preceding, in the order, the tail part. A queue controller retrieves LL elements in the head part from the first memory device, moves LL elements in the middle part from the second memory device to the head part in the first memory device prior to the head part becoming empty, and updates LL parameters corresponding to the moved LL elements to indicate storage of the moved LL elements changing from the second memory device to the first memory device.

Abstract: A network device and a method for maintaining a count of network events in a network device are provided. A first memory is configured as a first counter, where the first counter is configured to store a least significant bit (LSb) portion of a count value. A second memory is configured as a second counter, where the second counter is configured to store a most significant bit (MSb) portion of the count value. Update circuitry is configured to (i) selectively increment or decrement the LSb portion of the count value stored in the first memory upon occurrence of an event, and (ii) selectively increment or decrement the MSb portion of the count value stored in the second memory upon occurrence of a wrap-around event in the first memory.

Abstract: An arbiter device, during a given clock cycle, determines an ordered set corresponding to a plurality of first interfaces. The ordered set indicates whether each first interfaces of the plurality of first interfaces is available for selection for a second interface of a plurality of second interfaces during the given clock cycle. The arbiter device, during the given clock cycle, selects a respective available first interface, from the ordered set corresponding to the plurality of first interfaces, for each of the plurality of second interfaces. Selecting an available first interface for a particular one of the second interfaces is performed in parallel with and independently from selecting available first interfaces for other ones of the second interfaces. The arbiter device, during the given clock cycle, generates an output that indicates the selections of the respective first interfaces for the second interfaces.

Abstract: A First-In-First-Out (FIFO) system and a method for providing access to a memory shared by a plurality of N clients are provided. The memory has a single memory space for holding a plurality of data storage arrays that are respectively configured to store data in a first-in-first-out manner for corresponding clients among the N clients. An arbiter is configured to receive memory access requests from two or more of the N clients to perform a FIFO operation, to push data into a corresponding storage array or to pop data from the corresponding storage array in response to the memory access request. The arbiter is configured to select a first at least one of the clients to perform a first FIFO operation in a first memory operation cycle and to select a second at least one of the clients to perform a second FIFO operation in a second memory operation cycle.

Abstract: A method for data storage includes receiving one or more read commands and one or more write commands, for execution in a same clock cycle in a memory array that comprises multiple single-port memory banks divided into groups. The write commands provide data for storage but do not specify storage locations in which the data is to be stored. One or more of the groups, which are not accessed by the read commands in the same clock cycle, are selected. Available storage locations are chosen for the write commands in the single-port memory banks of the selected one or more groups. During the same clock cycle, the data provided in the write commands is stored in the chosen storage locations, and the data requested by the read commands is retrieved. Execution of the write commands is acknowledged by reporting the chosen storage locations.

Abstract: A plurality of physical queues, in a memory of a network device, are logically coupled to define a logical queue. Packets are received by the network device, and respective data units associated with the packets are distributed to the plurality of physical queues for storage according to a predetermined scheme i) to alternate among the plurality of physical queues, and ii) to maintain an order of data units stored in the logical queue. The data units are retrieved from the plurality of physical queues according to the predetermined scheme i) to alternate among the plurality of physical queues, and ii) to maintain the order of the data units.

Abstract: Data items to be stored in a queue are received, where the queue is distributed among a plurality of memory banks. The data items are distributed among the plurality of memory banks, including selecting memory banks in which to store the data items based on pseudorandom numbers generated for the data items, where the pseudorandom numbers are generated using a first pseudorandom number generator initialized with a first seed. Subsequently the data items are retrieved from the plurality of memory banks, including selecting memory banks from which to retrieve the data items based on the pseudorandom numbers regenerated for the data items, where the pseudorandom numbers are regenerated using a second pseudorandom number generator initialized with the first seed.

Abstract: A memory device includes content banks configured to store content data and parity banks configured to store parity data for reconstructing the content data. In response to receiving, in a first clock cycle, a first request requesting a first operation to be performed in a first content bank and a second request requesting to write new content data to the first content bank, the memory device performs the first operation in the first content bank, and writes the new content data to a second content bank. The second content bank is selected from a subset of content banks defined by content banks that correspond with parity banks different from parity banks that correspond with the first content bank. The memory device updates, based on the new content data written to the second content bank, parity data in the parity banks that correspond with the second content bank.

Abstract: A first memory device stores (i) a head part of a FIFO queue structured as a linked list (LL) of LL elements arranged in an order in which the LL elements were added to the FIFO queue and (ii) a tail part of the FIFO queue. A second memory device stores a middle part of the FIFO queue, the middle part comprising a LL elements following, in an order, the head part and preceding, in the order, the tail part. A queue controller retrieves LL elements in the head part from the first memory device, moves LL elements in the middle part from the second memory device to the head part in the first memory device prior to the head part becoming empty, and updates LL parameters corresponding to the moved LL elements to indicate storage of the moved LL elements changing from the second memory device to the first memory device.

Abstract: In a method for queuing data units in a network device, a plurality of physical queues corresponding to a port of the network device are defined in a memory of the network device. Respective subsets of the plurality of physical queues are logically coupled to define a plurality of logical queues that are respectively formed of logically coupled physical queues. The logical queues correspond to respective data flows of the port. A data unit belonging to a data flow is received. A logical queue for storing the data unit is selected, based on the data flow of the data unit, from the plurality of logical queues The A physical queue for storing the data unit is then selected from the subset of physical queues that corresponds to the selected logical queue. The data unit is stored in the selected physical queue.

Abstract: A method for data storage includes receiving one or more read commands and one or more write commands, for execution in a same clock cycle in a memory array that comprises multiple single-port memory banks divided into groups. The write commands provide data for storage but do not specify storage locations in which the data is to be stored. One or more of the groups, which are not accessed by the read commands in the same clock cycle, are selected. Available storage locations are chosen for the write commands in the single-port memory banks of the selected one or more groups. During the same clock cycle, the data provided in the write commands is stored in the chosen storage locations, and the data requested by the read commands is retrieved. Execution of the write commands is acknowledged by reporting the chosen storage locations.

Abstract: A memory supports a write or multiple read operations in any given clock cycle. In a first clock cycle, new content data is written to a particular content memory bank among a set of content memory banks. Also in the first clock cycle, current content data is read from corresponding locations in one or more other content memory banks among the set of content memory banks. New parity data is generated based on the new content data written to the particular content memory bank and the current content data read from the one or more other content memory banks. The new parity data is written to a cache memory associated with the one or more parity banks. In a second clock cycle subsequent to the first clock cycle, the new parity data is transferred from the cache memory to one of the one or more parity memory banks.

Abstract: A method for data storage includes, in a network element, receiving from packet-processing circuitry at least a read command and a write command, for execution in a memory array that includes multiple single-port memory banks. When the read command and the write command are to access different memory banks in the memory array, the read command and the write command are executed for the packet-processing circuitry in the different memory banks in a same memory-access cycle. When the read command and the write command are both to access a first memory bank, a second memory bank of the memory array is selected. The read command is executed in the first memory bank and the write command is executed in the second memory bank, in the same memory-access cycle.

Abstract: A method includes receiving a plurality of requests, determining a plurality of first bank identifiers specifying respective physical memory banks, and selecting, based at least on the first bank identifiers, a first set of requests to be processed according to a scheduling hierarchy. Selecting the first set of requests includes prohibiting any two requests from being associated with a same first bank identifier. The method also includes processing, during a single processing cycle, ones of the first set of requests at respective nodes within a single level of the scheduling hierarchy. The method also includes, responsively at least to processing ones of the first set of requests at respective nodes within the single level of the scheduling hierarchy, selecting a queue, and, responsively at least to selecting the queue, causing one or more packets corresponding to a traffic class associated with the queue to be sent to an egress port.

Abstract: In a method of managing queues in an egress queuing system in a network device, a plurality of packets to be stored in a first egress queue are received. The first egress queue is distributed among a plurality of memory banks. The packets are distributed among the plurality of memory banks. Memory banks in which to store the packets are selected based on pseudorandom numbers generated for the packets. The pseudorandom numbers are generated using a first pseudorandom number generator initialized with a first seed. Subsequently, the packets are retrieved from the plurality of memory banks. Memory banks from which to retrieve the packets are selected based on pseudorandom numbers regenerated for the packets. The pseudorandom numbers are regenerated using a second pseudorandom number generator initialized with the first seed.

Abstract: Described herein are memory apparatuses, and methods of operating the same, that have a memory array module configured, in a given clock cycle, to either receive a first command to write to a first memory location having a first address, or receive a second command to read from a second memory location having a second address. A comparison circuit of the memory apparatus is configured to compare the first address to the second address. The memory apparatus also includes an output circuit configured to output data stored in the memory array module at the second memory location based at least on the first address and second address being different. The output circuit is also configured to output data received from a write data input, bypassing the memory array module, when the first address and the second address are the same.