Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

Abstract: A system and method for preventing an application program, which is licensed to a customer to be exclusively executed in a processor based on a certain processor design, from being executed properly in unauthorized processors is provided. The system includes a scrambling module and a recovery module. The scrambling module scrambles a selected portion of the application program using an identifier which identifies the authorized processor design. The recovery module adds an unscrambling program to the application program such that when the program is running in a processor, it retrieves a second identifier from the processor and unscrambles the scrambled portion of the application program using the retrieved second identifier. If the second identifier does not correspond to an authorized processor design, the unscrambling operation will incorrectly unscramble the scrambled portion and the application program will not run properly.

Abstract: A microprocessor includes a memory interface to obtain data envelopes of a first length, and control logic to implement an instruction to load an initial data envelope of a stream of data values into a buffer, each data value having a second length shorter than the first length, the stream of data values being disposed across successive data envelopes at the memory interface. Another instruction merges current contents of the buffer and the memory interface such that each invocation loads one of the data values into a first register, and moves at least a remainder of the current contents of the memory interface into the buffer for use in a successive invocation. Another instruction loads a reversed representation of a set of data values obtained via the memory interface into a second register. Another instruction implements an FIR computation including a SIMD operation involving multiple data values of the stream and the reversed representation.

Abstract: A microprocessor includes a memory interface to obtain data envelopes of a first length, and control logic to implement an instruction to load an initial data envelope of a stream of data values into a buffer, each data value having a second length shorter than the first length, the stream of data values being disposed across successive data envelopes at the memory interface. Another instruction merges current contents of the buffer and the memory interface such that each invocation loads one of the data values into a first register, and moves at least a remainder of the current contents of the memory interface into the buffer for use in a successive invocation. Another instruction loads a reversed representation of a set of data values obtained via the memory interface into a second register. Another instruction implements an FIR computation including a SIMD operation involving multiple data values of the stream and the reversed representation.

Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

Abstract: A system and method for preventing an application program, which is licensed to a customer to be exclusively executed in a processor based on a certain processor design, from being executed properly in unauthorized processors is provided. The system includes a scrambling module and a recovery module. The scrambling module scrambles a selected portion of the application program using an identifier which identifies the authorized processor design. The recovery module adds an unscrambling program to the application program such that when the program is running in a processor, it retrieves a second identifier from the processor and unscrambles the scrambled portion of the application program using the retrieved second identifier. If the second identifier does not correspond to an authorized processor design, the unscrambling operation will incorrectly unscramble the scrambled portion and the application program will not run properly.

Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

Abstract: A method for decomposing a target pattern containing features to be printed on a wafer into multiple patterns. The method includes the steps of segmenting the target pattern into a plurality of patches; identifying critical features within each patch which violate minimum spacing requirements; generating a critical group graph for each of the plurality of patches having critical features, where the critical group graph of a given patch defines a coloring scheme of the critical features within the given patch, and the critical group graph identifies critical features extending into adjacent patches to the given patch; generating a global critical group graph for the target pattern, where the global critical group graph includes the critical group graphs of each of the plurality of patches, and an identification of the features extending into adjacent patches; and coloring the target pattern based on the coloring scheme defined by the global critical group graph.

Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

Abstract: In selecting and building a processor configuration, a user creates a new set of user-defined instructions, places them in a file directory, and invokes a tool that processes the user instructions and transforms them into a form usable by the software development tools. The user then invokes the software development tools, telling the tools to dynamically use the instructions created in the new directory. In this way, the user may customize a processor configuration by adding new instructions and within minutes, be able to evaluate that feature. The user is able to keep multiple sets of potential instructions and easily switch between them when evaluating their application.

Abstract: In a computer system having a cache memory and a main memory for storing data, a method for laying out blocks of data to minimize a number of memory transfers between the cache memory and the main memory. Memory layout normally occurs at link time, after all the source files have been compiled. The code is compiled with the assumption that the memory blocks can be optimally placed. The linker then determines whether there has been any memory violations. Memory violations are marked. All marked memory locations are then placed in a layout that satisfies adjacency requirements.