Patents by Inventor Dror Goldenberg
Dror Goldenberg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11934658Abstract: A peripheral device includes a host interface and processing circuitry. The host interface is to communicate with one or more hosts over a peripheral bus. The processing circuitry is to expose on the peripheral bus a peripheral-bus device that communicates with the one or more hosts using one or more instances of at least one bus storage protocol, to receive, using the exposed peripheral-bus device, Input/Output (I/O) transactions that are issued by the one or more hosts, and to complete the I/O transactions for the one or more hosts in accordance with one or more instances of at least one network storage protocol, by running at least part of a host-side protocol stack of the at least one network storage protocol.Type: GrantFiled: November 16, 2021Date of Patent: March 19, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Boris Pismenny, Oren Duer, Dror Goldenberg
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Patent number: 11934333Abstract: A peripheral device includes a host interface and processing circuitry. The host interface is configured to communicate with a host over a peripheral bus. The processing circuitry is configured to expose on the peripheral bus a peripheral-bus device that communicates with the host using a bus storage protocol, to receive, using the exposed peripheral-bus device, Input/Output (I/O) transactions that are issued by the host, and to complete the I/O transactions for the host in accordance with a network storage protocol, by running at least part of a host-side protocol stack of the network storage protocol.Type: GrantFiled: March 25, 2021Date of Patent: March 19, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Oren Duer, Dror Goldenberg
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Patent number: 11892964Abstract: A peripheral device includes a host interface and processing circuitry. The host interface is configured to communicate with a host over a peripheral bus. The processing circuitry is configured to expose on the peripheral bus a peripheral-bus device that communicates with the host using a bus storage protocol, to receive, using the exposed peripheral-bus device, Input/Output (I/O) transactions that are issued by the host, and to complete the I/O transactions for the host in accordance with a network storage protocol, by running at least part of a host-side protocol stack of the network storage protocol.Type: GrantFiled: March 25, 2021Date of Patent: February 6, 2024Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Oren Duer, Dror Goldenberg
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Publication number: 20230379390Abstract: Apparatus for data communication includes a network interface for connection to a packet data network and a host interface for connection to a host computer, which includes a central processing unit (CPU) and a host memory. Packet processing circuitry receives, via the host interface, from a kernel running on the CPU, associations between multiple remote direct memory access (RDMA) sessions and multiple different User Datagram Protocol (UDP) 5-tuple, which are assigned respectively to the RDMA sessions, and receives from an application running on the CPU a request to send an RDMA message, using a selected group of one or more of the RDMA sessions, to a peer application over the packet data network, and in response to the request, transmits, via the network interface, one or more data packets using a UDP 5-tuple that is assigned to one of the RDMA sessions in the selected group.Type: ApplicationFiled: August 1, 2023Publication date: November 23, 2023Inventors: Liran Liss, Yamin Friedman, Michael Kagan, Diego Crupnicoff, Idan Burstein, Matty Kadosh, Tzah Oved, Dror Goldenberg, Ron Yuval Efraim, Alexander Eli Rosenbaum, Aviad Yehezkel, Rabia Loulou
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Publication number: 20230353419Abstract: A cross-network bridging apparatus includes a bus interface and bridging circuitry. The bus interface is configured for connecting to a system bus. The bridging circuitry is configured to translate between (i) system-bus transactions that are exchanged between one or more local devices that are coupled to the system bus and served by the system bus and one or more remote processors located across a network from the apparatus, and (ii) data units that convey the system-bus transactions, for transmitting and receiving as network packets over the network to and from the remote processors.Type: ApplicationFiled: July 9, 2023Publication date: November 2, 2023Inventors: Daniel Marcovitch, Idan Burstein, Liran Liss, Hillel Chapman, Dror Goldenberg, Michael Kagan, Aviad Yehezkel, Peter Paneah
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Patent number: 11765237Abstract: Apparatus for data communication includes a network interface for connection to a packet data network and a host interface for connection to a host computer, which includes a central processing unit (CPU) and a host memory. Packet processing circuitry receives, via the host interface, from a kernel running on the CPU, associations between multiple remote direct memory access (RDMA) sessions and multiple different User Datagram Protocol (UDP) 5-tuple, which are assigned respectively to the RDMA sessions, and receives from an application running on the CPU a request to send an RDMA message, using a selected group of one or more of the RDMA sessions, to a peer application over the packet data network, and in response to the request, transmits, via the network interface, one or more data packets using a UDP 5-tuple that is assigned to one of the RDMA sessions in the selected group.Type: GrantFiled: April 20, 2022Date of Patent: September 19, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Liran Liss, Yamin Friedman, Michael Kagan, Diego Crupnicoff, Idan Burstein, Matty Kadosh, Tzah Oved, Dror Goldenberg, Ron Yuval Efraim, Alexander Eli Rosenbaum, Aviad Yehezkel, Rabia Loulou
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Patent number: 11750418Abstract: A cross-network bridging apparatus includes a bus interface and bridging circuitry. The bus interface is configured for connecting to a system bus. The bridging circuitry is configured to translate between (i) system-bus transactions that are exchanged between one or more local devices that are coupled to the system bus and served by the system bus and one or more remote processors located across a network from the apparatus, and (ii) data units that convey the system-bus transactions, for transmitting and receiving as network packets over the network to and from the remote processors.Type: GrantFiled: September 7, 2020Date of Patent: September 5, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Daniel Marcovitch, Idan Burstein, Liran Liss, Hillel Chapman, Dror Goldenberg, Michael Kagan, Aviad Yehezkel, Peter Paneah
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Publication number: 20220308764Abstract: A peripheral device includes a host interface and processing circuitry. The host interface is to communicate with one or more hosts over a peripheral bus. The processing circuitry is to expose on the peripheral bus a peripheral-bus device that communicates with the one or more hosts using one or more instances of at least one bus storage protocol, to receive, using the exposed peripheral-bus device, Input/Output (I/O) transactions that are issued by the one or more hosts, and to complete the I/O transactions for the one or more hosts in accordance with one or more instances of at least one network storage protocol, by running at least part of a host-side protocol stack of the at least one network storage protocol.Type: ApplicationFiled: November 16, 2021Publication date: September 29, 2022Inventors: Boris Pismenny, Oren Duer, Dror Goldenberg
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Publication number: 20220309019Abstract: A peripheral device includes a host interface and processing circuitry. The host interface is configured to communicate with a host over a peripheral bus. The processing circuitry is configured to expose on the peripheral bus a peripheral-bus device that communicates with the host using a bus storage protocol, to receive, using the exposed peripheral-bus device, Input/Output (I/O) transactions that are issued by the host, and to complete the I/O transactions for the host in accordance with a network storage protocol, by running at least part of a host-side protocol stack of the network storage protocol.Type: ApplicationFiled: March 25, 2021Publication date: September 29, 2022Inventors: Oren Duer, Dror Goldenberg
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Patent number: 11336508Abstract: A network interface apparatus includes a host interface for connection to a host processor and a network interface, which includes multiple distinct physical ports. Processing circuitry associates each of a plurality of virtual entities running on the host processor with a respective one of the physical ports, so that while both of the first and second physical ports are operational, the processing circuitry transmits data packets on behalf of first and second virtual entities, using assigned upper-layer addresses, through associated first and second physical ports. In response to an indication that the first physical port has ceased to operate, the processing circuitry transmits the data packets on behalf of the first virtual entity through the second physical port without changing the upper-layer addresses.Type: GrantFiled: July 1, 2018Date of Patent: May 17, 2022Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Ron Efraim, Dror Goldenberg
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Publication number: 20220078043Abstract: A cross-network bridging apparatus includes a bus interface and bridging circuitry. The bus interface is configured for connecting to a system bus. The bridging circuitry is configured to translate between (i) system-bus transactions that are exchanged between one or more local devices that are coupled to the system bus and served by the system bus and one or more remote processors located across a network from the apparatus, and (ii) data units that convey the system-bus transactions, for transmitting and receiving as network packets over the network to and from the remote processors.Type: ApplicationFiled: September 7, 2020Publication date: March 10, 2022Inventors: Daniel Marcovitch, Idan Burstein, Liran Liss, Hillel Chapman, Dror Goldenberg, Michael Kagan, Aviad Yehezkel, Peter Paneah
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Publication number: 20200007383Abstract: A network interface apparatus includes a host interface for connection to a host processor and a network interface, which includes multiple distinct physical ports. Processing circuitry associates each of a plurality of virtual entities running on the host processor with a respective one of the physical ports, so that while both of the first and second physical ports are operational, the processing circuitry transmits data packets on behalf of first and second virtual entities, using assigned upper-layer addresses, through associated first and second physical ports. In response to an indication that the first physical port has ceased to operate, the processing circuitry transmits the data packets on behalf of the first virtual entity through the second physical port without changing the upper-layer addresses.Type: ApplicationFiled: July 1, 2018Publication date: January 2, 2020Inventors: Ron Efraim, Dror Goldenberg
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Patent number: 10404530Abstract: Computerized methods and systems are disclosed for configuring a network controller (NC). These methods and systems recognize, via a network device, e.g., hardware, software, processors, storage media, memory, a predetermined command from a management controller (MC). The network device responds to the predetermined command by configuring the NC with a message type associated with an event, and controlling enablement of a message associated with the message type using a selectable enable bit as defined in the predetermined command.Type: GrantFiled: November 6, 2014Date of Patent: September 3, 2019Assignee: Mellanox Technologes, Ltd.Inventors: Yuval Itkin, Dror Goldenberg
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Patent number: 10382396Abstract: A network connection device having a security processor exchanges data traffic between a data network and a host computer via a network port. Security management data is exchanged exclusively between the security processor and a management network via a management network connectivity port that is inaccessible to the data traffic.Type: GrantFiled: December 28, 2016Date of Patent: August 13, 2019Assignee: Mellanox Technologies, Ltd.Inventors: Yuval Itkin, Tal Anker, Dror Goldenberg
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Patent number: 10148746Abstract: A network adapter includes one or more ports and circuitry. The ports are configured to connect to a switch in a communication network. The circuitry is coupled to a network node that includes multiple hosts, and is configured to exchange management packets between a control server and multiple BMC units associated respectively with the multiple hosts, and to exchange, over the communication network via the one or more ports, data packets between the hosts and one or more remote nodes.Type: GrantFiled: December 25, 2014Date of Patent: December 4, 2018Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Yuval Itkin, Noam Bloch, Dror Goldenberg
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Publication number: 20180183758Abstract: A network connection device having a security processor exchanges data traffic between a data network and a host computer via a network port. Security management data is exchanged exclusively between the security processor and a management network via a management network connectivity port that is inaccessible to the data traffic.Type: ApplicationFiled: December 28, 2016Publication date: June 28, 2018Inventors: Yuval Itkin, Tal Anker, Dror Goldenberg
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Patent number: 10009277Abstract: Communication apparatus includes a plurality of interfaces configured to be connected to a Layer-3 packet network and to serve as ingress and egress interfaces to receive and transmit packets from and to the network. Routing logic is coupled to process respective Layer-3 headers of the packets received through the ingress interfaces and to route the packets via the egress interfaces to respective destinations indicated by the Layer-3 headers. Congestion detection logic is coupled to identify a flow of the received packets that is causing congestion in the network and a Layer-3 address from which the flow originates, and to direct the routing logic to route a backward congestion notification message (CNM) packet via one of the egress interfaces to the identified Layer-3 address.Type: GrantFiled: August 2, 2016Date of Patent: June 26, 2018Assignee: Mellanox Technologies TLV Ltd.Inventors: Dror Goldenberg, Alex Shpiner, Gil Levy, Barak Gafni, Shachar Raindel
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Patent number: 10009278Abstract: A method for designing a Network Function Virtualization (NFV) architecture includes accepting a definition of multiple Virtual Network Functions (VNFs), and of one or more packet types having respective occurrence probabilities, wherein each packet type is associated with a respective subset of the VNFs that are to be applied to packets of that packet type. Information on multiple available physical computers, each capable of running only a partial subset of the multiple VNFs, is further accepted. The VNFs are allocated to the physical computers by applying an optimality criterion to definition and the information.Type: GrantFiled: February 9, 2015Date of Patent: June 26, 2018Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Ori Rottenstreich, Dror Goldenberg
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Patent number: 9998359Abstract: A method in a network node that includes a network adapter, a Baseboard Management Controller (BMC) and a host, includes connecting to a switch in a communication network using first and second ports of the network adapter, as member ports of a Link Aggregation Group (LAG). Management and data packets are simultaneously exchanged over the communication network via the LAG member ports, so that the management packets are exchanged between the BMC and a control server, and the data packets between the host and a remote node.Type: GrantFiled: November 19, 2014Date of Patent: June 12, 2018Assignee: Mellanox Technologies, Ltd.Inventors: Yuval Itkin, Dror Goldenberg
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Patent number: 9894005Abstract: A method in a network element that includes multiple interfaces for connecting to a communication network includes receiving from the communication network via an ingress interface a flow including a sequence of packets, and routing the packets to a destination of the flow via a first egress interface. A permission indication for re-routing the flow is received in the ingress interface. In response to receiving the permission indication, subsequent packets of the flow are re-routed via a second egress interface that is different from the first egress interface. Further re-routing of the flow is refrained from, until receiving another permission indication.Type: GrantFiled: March 31, 2015Date of Patent: February 13, 2018Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Shachar Raindel, Idan Burstein, Noam Bloch, Benny Koren, Barak Gafni, Dror Goldenberg, Liran Liss