Patents by Inventor Dror Goldenberg

Dror Goldenberg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12244670
    Abstract: Apparatus for data communication includes a network interface for connection to a packet data network and a host interface for connection to a host computer, which includes a central processing unit (CPU) and a host memory. Packet processing circuitry receives, via the host interface, from a kernel running on the CPU, associations between multiple remote direct memory access (RDMA) sessions and multiple different User Datagram Protocol (UDP) 5-tuple, which are assigned respectively to the RDMA sessions, and receives from an application running on the CPU a request to send an RDMA message, using a selected group of one or more of the RDMA sessions, to a peer application over the packet data network, and in response to the request, transmits, via the network interface, one or more data packets using a UDP 5-tuple that is assigned to one of the RDMA sessions in the selected group.
    Type: Grant
    Filed: August 1, 2023
    Date of Patent: March 4, 2025
    Assignee: Mellanox Technologies, Ltd
    Inventors: Liran Liss, Yamin Friedman, Michael Kagan, Diego Crupnicoff, Idan Burstein, Matty Kadosh, Tzah Oved, Dror Goldenberg, Ron Yuval Efraim, Alexander Eli Rosenbaum, Aviad Yehezkel, Rabia Loulou
  • Patent number: 12119958
    Abstract: A cross-network bridging apparatus includes a bus interface and bridging circuitry. The bus interface is configured for connecting to a system bus. The bridging circuitry is configured to translate between (i) system-bus transactions that are exchanged between one or more local devices that are coupled to the system bus and served by the system bus and one or more remote processors located across a network from the apparatus, and (ii) data units that convey the system-bus transactions, for transmitting and receiving as network packets over the network to and from the remote processors.
    Type: Grant
    Filed: July 9, 2023
    Date of Patent: October 15, 2024
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Daniel Marcovitch, Idan Burstein, Liran Liss, Hillel Chapman, Dror Goldenberg, Michael Kagan, Aviad Yehezkel, Peter Paneah
  • Publication number: 20240340197
    Abstract: A cross-network bridging apparatus includes a bus interface and bridging circuitry. The bus interface is configured for connecting to a system bus. The bridging circuitry is configured to translate between (i) system-bus transactions that are exchanged between one or more local devices that are coupled to the system bus and served by the system bus and one or more remote processors located across a network from the apparatus, and (ii) data units that convey the system-bus transactions, for transmitting and receiving as network packets over the network to and from the remote processors.
    Type: Application
    Filed: June 16, 2024
    Publication date: October 10, 2024
    Inventors: Daniel Marcovitch, Idan Burstein, Liran Liss, Hillel Chapman, Dror Goldenberg, Michael Kagan, Aviad Yehezkel, Peter Paneah
  • Patent number: 11934658
    Abstract: A peripheral device includes a host interface and processing circuitry. The host interface is to communicate with one or more hosts over a peripheral bus. The processing circuitry is to expose on the peripheral bus a peripheral-bus device that communicates with the one or more hosts using one or more instances of at least one bus storage protocol, to receive, using the exposed peripheral-bus device, Input/Output (I/O) transactions that are issued by the one or more hosts, and to complete the I/O transactions for the one or more hosts in accordance with one or more instances of at least one network storage protocol, by running at least part of a host-side protocol stack of the at least one network storage protocol.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: March 19, 2024
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Boris Pismenny, Oren Duer, Dror Goldenberg
  • Patent number: 11934333
    Abstract: A peripheral device includes a host interface and processing circuitry. The host interface is configured to communicate with a host over a peripheral bus. The processing circuitry is configured to expose on the peripheral bus a peripheral-bus device that communicates with the host using a bus storage protocol, to receive, using the exposed peripheral-bus device, Input/Output (I/O) transactions that are issued by the host, and to complete the I/O transactions for the host in accordance with a network storage protocol, by running at least part of a host-side protocol stack of the network storage protocol.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: March 19, 2024
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Oren Duer, Dror Goldenberg
  • Patent number: 11892964
    Abstract: A peripheral device includes a host interface and processing circuitry. The host interface is configured to communicate with a host over a peripheral bus. The processing circuitry is configured to expose on the peripheral bus a peripheral-bus device that communicates with the host using a bus storage protocol, to receive, using the exposed peripheral-bus device, Input/Output (I/O) transactions that are issued by the host, and to complete the I/O transactions for the host in accordance with a network storage protocol, by running at least part of a host-side protocol stack of the network storage protocol.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: February 6, 2024
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Oren Duer, Dror Goldenberg
  • Publication number: 20230379390
    Abstract: Apparatus for data communication includes a network interface for connection to a packet data network and a host interface for connection to a host computer, which includes a central processing unit (CPU) and a host memory. Packet processing circuitry receives, via the host interface, from a kernel running on the CPU, associations between multiple remote direct memory access (RDMA) sessions and multiple different User Datagram Protocol (UDP) 5-tuple, which are assigned respectively to the RDMA sessions, and receives from an application running on the CPU a request to send an RDMA message, using a selected group of one or more of the RDMA sessions, to a peer application over the packet data network, and in response to the request, transmits, via the network interface, one or more data packets using a UDP 5-tuple that is assigned to one of the RDMA sessions in the selected group.
    Type: Application
    Filed: August 1, 2023
    Publication date: November 23, 2023
    Inventors: Liran Liss, Yamin Friedman, Michael Kagan, Diego Crupnicoff, Idan Burstein, Matty Kadosh, Tzah Oved, Dror Goldenberg, Ron Yuval Efraim, Alexander Eli Rosenbaum, Aviad Yehezkel, Rabia Loulou
  • Publication number: 20230353419
    Abstract: A cross-network bridging apparatus includes a bus interface and bridging circuitry. The bus interface is configured for connecting to a system bus. The bridging circuitry is configured to translate between (i) system-bus transactions that are exchanged between one or more local devices that are coupled to the system bus and served by the system bus and one or more remote processors located across a network from the apparatus, and (ii) data units that convey the system-bus transactions, for transmitting and receiving as network packets over the network to and from the remote processors.
    Type: Application
    Filed: July 9, 2023
    Publication date: November 2, 2023
    Inventors: Daniel Marcovitch, Idan Burstein, Liran Liss, Hillel Chapman, Dror Goldenberg, Michael Kagan, Aviad Yehezkel, Peter Paneah
  • Patent number: 11765237
    Abstract: Apparatus for data communication includes a network interface for connection to a packet data network and a host interface for connection to a host computer, which includes a central processing unit (CPU) and a host memory. Packet processing circuitry receives, via the host interface, from a kernel running on the CPU, associations between multiple remote direct memory access (RDMA) sessions and multiple different User Datagram Protocol (UDP) 5-tuple, which are assigned respectively to the RDMA sessions, and receives from an application running on the CPU a request to send an RDMA message, using a selected group of one or more of the RDMA sessions, to a peer application over the packet data network, and in response to the request, transmits, via the network interface, one or more data packets using a UDP 5-tuple that is assigned to one of the RDMA sessions in the selected group.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: September 19, 2023
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Liran Liss, Yamin Friedman, Michael Kagan, Diego Crupnicoff, Idan Burstein, Matty Kadosh, Tzah Oved, Dror Goldenberg, Ron Yuval Efraim, Alexander Eli Rosenbaum, Aviad Yehezkel, Rabia Loulou
  • Patent number: 11750418
    Abstract: A cross-network bridging apparatus includes a bus interface and bridging circuitry. The bus interface is configured for connecting to a system bus. The bridging circuitry is configured to translate between (i) system-bus transactions that are exchanged between one or more local devices that are coupled to the system bus and served by the system bus and one or more remote processors located across a network from the apparatus, and (ii) data units that convey the system-bus transactions, for transmitting and receiving as network packets over the network to and from the remote processors.
    Type: Grant
    Filed: September 7, 2020
    Date of Patent: September 5, 2023
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Daniel Marcovitch, Idan Burstein, Liran Liss, Hillel Chapman, Dror Goldenberg, Michael Kagan, Aviad Yehezkel, Peter Paneah
  • Publication number: 20220308764
    Abstract: A peripheral device includes a host interface and processing circuitry. The host interface is to communicate with one or more hosts over a peripheral bus. The processing circuitry is to expose on the peripheral bus a peripheral-bus device that communicates with the one or more hosts using one or more instances of at least one bus storage protocol, to receive, using the exposed peripheral-bus device, Input/Output (I/O) transactions that are issued by the one or more hosts, and to complete the I/O transactions for the one or more hosts in accordance with one or more instances of at least one network storage protocol, by running at least part of a host-side protocol stack of the at least one network storage protocol.
    Type: Application
    Filed: November 16, 2021
    Publication date: September 29, 2022
    Inventors: Boris Pismenny, Oren Duer, Dror Goldenberg
  • Publication number: 20220309019
    Abstract: A peripheral device includes a host interface and processing circuitry. The host interface is configured to communicate with a host over a peripheral bus. The processing circuitry is configured to expose on the peripheral bus a peripheral-bus device that communicates with the host using a bus storage protocol, to receive, using the exposed peripheral-bus device, Input/Output (I/O) transactions that are issued by the host, and to complete the I/O transactions for the host in accordance with a network storage protocol, by running at least part of a host-side protocol stack of the network storage protocol.
    Type: Application
    Filed: March 25, 2021
    Publication date: September 29, 2022
    Inventors: Oren Duer, Dror Goldenberg
  • Patent number: 11336508
    Abstract: A network interface apparatus includes a host interface for connection to a host processor and a network interface, which includes multiple distinct physical ports. Processing circuitry associates each of a plurality of virtual entities running on the host processor with a respective one of the physical ports, so that while both of the first and second physical ports are operational, the processing circuitry transmits data packets on behalf of first and second virtual entities, using assigned upper-layer addresses, through associated first and second physical ports. In response to an indication that the first physical port has ceased to operate, the processing circuitry transmits the data packets on behalf of the first virtual entity through the second physical port without changing the upper-layer addresses.
    Type: Grant
    Filed: July 1, 2018
    Date of Patent: May 17, 2022
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Ron Efraim, Dror Goldenberg
  • Publication number: 20220078043
    Abstract: A cross-network bridging apparatus includes a bus interface and bridging circuitry. The bus interface is configured for connecting to a system bus. The bridging circuitry is configured to translate between (i) system-bus transactions that are exchanged between one or more local devices that are coupled to the system bus and served by the system bus and one or more remote processors located across a network from the apparatus, and (ii) data units that convey the system-bus transactions, for transmitting and receiving as network packets over the network to and from the remote processors.
    Type: Application
    Filed: September 7, 2020
    Publication date: March 10, 2022
    Inventors: Daniel Marcovitch, Idan Burstein, Liran Liss, Hillel Chapman, Dror Goldenberg, Michael Kagan, Aviad Yehezkel, Peter Paneah
  • Publication number: 20200007383
    Abstract: A network interface apparatus includes a host interface for connection to a host processor and a network interface, which includes multiple distinct physical ports. Processing circuitry associates each of a plurality of virtual entities running on the host processor with a respective one of the physical ports, so that while both of the first and second physical ports are operational, the processing circuitry transmits data packets on behalf of first and second virtual entities, using assigned upper-layer addresses, through associated first and second physical ports. In response to an indication that the first physical port has ceased to operate, the processing circuitry transmits the data packets on behalf of the first virtual entity through the second physical port without changing the upper-layer addresses.
    Type: Application
    Filed: July 1, 2018
    Publication date: January 2, 2020
    Inventors: Ron Efraim, Dror Goldenberg
  • Patent number: 10404530
    Abstract: Computerized methods and systems are disclosed for configuring a network controller (NC). These methods and systems recognize, via a network device, e.g., hardware, software, processors, storage media, memory, a predetermined command from a management controller (MC). The network device responds to the predetermined command by configuring the NC with a message type associated with an event, and controlling enablement of a message associated with the message type using a selectable enable bit as defined in the predetermined command.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: September 3, 2019
    Assignee: Mellanox Technologes, Ltd.
    Inventors: Yuval Itkin, Dror Goldenberg
  • Patent number: 10382396
    Abstract: A network connection device having a security processor exchanges data traffic between a data network and a host computer via a network port. Security management data is exchanged exclusively between the security processor and a management network via a management network connectivity port that is inaccessible to the data traffic.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: August 13, 2019
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Yuval Itkin, Tal Anker, Dror Goldenberg
  • Patent number: 10148746
    Abstract: A network adapter includes one or more ports and circuitry. The ports are configured to connect to a switch in a communication network. The circuitry is coupled to a network node that includes multiple hosts, and is configured to exchange management packets between a control server and multiple BMC units associated respectively with the multiple hosts, and to exchange, over the communication network via the one or more ports, data packets between the hosts and one or more remote nodes.
    Type: Grant
    Filed: December 25, 2014
    Date of Patent: December 4, 2018
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Yuval Itkin, Noam Bloch, Dror Goldenberg
  • Publication number: 20180183758
    Abstract: A network connection device having a security processor exchanges data traffic between a data network and a host computer via a network port. Security management data is exchanged exclusively between the security processor and a management network via a management network connectivity port that is inaccessible to the data traffic.
    Type: Application
    Filed: December 28, 2016
    Publication date: June 28, 2018
    Inventors: Yuval Itkin, Tal Anker, Dror Goldenberg
  • Patent number: 10009277
    Abstract: Communication apparatus includes a plurality of interfaces configured to be connected to a Layer-3 packet network and to serve as ingress and egress interfaces to receive and transmit packets from and to the network. Routing logic is coupled to process respective Layer-3 headers of the packets received through the ingress interfaces and to route the packets via the egress interfaces to respective destinations indicated by the Layer-3 headers. Congestion detection logic is coupled to identify a flow of the received packets that is causing congestion in the network and a Layer-3 address from which the flow originates, and to direct the routing logic to route a backward congestion notification message (CNM) packet via one of the egress interfaces to the identified Layer-3 address.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: June 26, 2018
    Assignee: Mellanox Technologies TLV Ltd.
    Inventors: Dror Goldenberg, Alex Shpiner, Gil Levy, Barak Gafni, Shachar Raindel