Abstract: An arrangement (200) and method for bit exactness support in dual-MAC architecture by detecting when underflow or overflow conditions will occur, and for operating the dual-MAC arrangement in single-MAC mode for at least one cycle upon such detection. This produces the advantages of providing dual-MAC execution with saturation capabilities, with only a small degradation in performance, while employing detection logic that is very small and simple compared to the logic required for a conventional full saturation dual-MAC architecture.

Abstract: A circuit selectively extracts bits from different locations from a source register and loads them in logical order in one side of a destination register. The register is divided into subsets. All of the transfer bits in each subset are arranged on one side and in logical order. These subsets are paired. The bits from one pair are shifted by an amount equal to the non-transfer bits from the other pair and then combined with the bits from the other pair to form a new group of bits that are on one side and are in logical order. The process of shifting bits of one of a pair of groups and combining with the other of the pair continues until all of the transfer bits from the source register are in one group on one side and in logical order.

Abstract: A circuit selectively extracts bits from different locations from a source register and loads them in logical order in one side of a destination register. The register is divided into subsets. All of the transfer bits in each subset are arranged on one side and in logical order. These subsets are paired. The bits from one pair are shifted by an amount equal to the non-transfer bits from the other pair and then combined with the bits from the other pair to form a new group of bits that are on one side and are in logical order. The process of shifting bits of one of a pair of groups and combining with the other of the pair continues until all of the transfer bits from the source register are in one group on one side and in logical order.

Abstract: An arrangement (200) and method for bit exactness support in dual-MAC architecture by detecting when underflow or overflow conditions will occur, and for operating the dual-MAC arrangement in single-MAC mode for at least one cycle upon such detection.

Abstract: Embodiments of the present invention relate generally to digital signal processing. One embodiment contemplates a method for performing a digital signal processing operation having a first data word located at a misaligned starting address within a first memory. The method includes outputting the first data word to a register file during a first internal. During a second interval, the method further includes reading a second data word and a third data word from the first memory where the second data word is output to the register file and the third data word is output to the first buffer. Embodiments also contemplate a digital signal processor having a register filed capable of receiving one data word from a memory and one data word from a buffer during each of a series of processing intervals for performing a digital signal operation.

Abstract: The invention relates to a digital signal processor in which two multiply accumulate operations are carried out in one machine cycle. Only one address generation unit is required for addressing two data words of both the X and Y memories, since in the main processing loop the least significant address bit is considered as "Don't care", so that an access operation to the memory results in two output data words at a time.

Abstract: An apparatus (12) and method (80, 120) is described for reducing power consumption in a system (10) having subsystems (34). A controller (40, 40', 40") detects the occurrence of a repetitive operation (62). The subsystems (34, 38) or a power down controller (39) detect (86, 128), whether a subset (60i) of the subsystems (34) is or is not participating in the repetitive operation (62). This preferably occurs during the first iteration (661-662) of the repetitive operation (62). Power controls (36) in or coupled to (39) the subsystems (34), reduce the power consumption of this subset (60i) of the subsystems (34) until the repetitive operation (62) is completed (642), whereupon power thereto is restored (114, 190). In the event of an interrupt (643-644), the subset (60i) is maintained (142) or returned (172) to full power operation until the interrupt (643-644) is finished (144, 174) and the repetitive operation resumes (644-642).

Abstract: DSP size and cost can be reduced by shrinking the program ROM and opcode interpreter (e.g., PLA) to store and recognize only #OC unique opcodes from within the total available opcodes for the DSP. The minimum opcode length M is the smallest integer satisfying 2.sup.M .gtoreq.#OC. It is preferred to choose an opcode length M'>M so that the total chip area occupied by the ROM plus PLA is minimized without loss of chip performance. By converting 24 bit opcodes to 16 bit opcodes for M=12 and M'=16, the combined program ROM and PLA areas are reduced by .about.1/3rd and the overall DSP is significantly smaller.

Abstract: A system rapidly dynamic values (B) on a bus (12) to a programmable but thereafter fixed reference value (C). The system includes first leads (33) coupled to a comparison means (35), second leads (13) coupled to the bus (12) and third leads (34, 36) coupled to sources of potential (GND, VCC) related to logical HIGH and LOW of the fixed reference value (C). The leads (33, 13, 34, 36) are coupled in one or more programmable connection cell (32). Connections (471) or disconnections (461) are made between the leads (33, 13, 34, 36) so that the dynamic values (B) and the appropriate logical HIGH and logical LOW values are presented to the correct inputs of the comparison means (35). The programmable connections cells (32) invert the reference value (C) to (C) for coupling to the comparator (35). The system replaces a level of conventional decode logic (16) by the programmable interconnections (47), thereby reducing delay time, using fewer devices and occupying less circuit area.